Measurement Computing PCI-DAS6052, Руководство пользователя

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PCI-DAS6052 User's Guide Functional Details
DAQ signal timing
The DAQ timing signals are:
ƒ SCANCLK
ƒ A/D START TRIGGER
ƒ A/D STOP TRIGGER
ƒ STARTSCAN
ƒ SSH
ƒ A/D CONVERT
ƒ A/D PACER GATE
ƒ A/D EXTERNAL TIME BASE
ƒ A/D STOP
ƒ ATRIG
SCANCLK signal
SCANCLK is an output signal that may be used for switching external multiplexers. It is
a 400 ns wide pulse that follows the CONVERT signal after a 50 ns delay. This is
adequate time for the analog input signal to be acquired so that the next signal may be
switched in. The polarity of the SCANCLK signal is programmable. The default output
pin for the SCANCLK signal is AUXOUT2, but any of the AUXOUT pins may be
programmed as a SCANCLK output.
CONVERT
SCANCLK
t
d
t
d
t
w
t
d
= 50 ns t
w
= 400 ns
Figure 4-2. SCANCLK Signal Timing
4-5