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PCI-DAS6052 User's Guide

Functional Details

Gate Negative Hysteresis

Data acquisition is enabled whenever ATRIG goes above the THRESH_HI level.
Acquisition is suspended whenever the ATRIG signal goes below the THRESH_LO
level. The hysteresis level is set by THRESH_LO. This is a level-sensitive gating mode.

Trigger

Acquired Data

+2

-2

+1

0

-1

Thresh_HI

+2

+1

0

-1

Thresh_LO

Figure 4-19. Gate Negative Hysteresis

4-17

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Содержание PCI-DAS6052

Страница 1: ...PCI DAS6052 Analog and Digital I O Board User s Guide Document Revision 2 November 2003 Copyright 2003 Measurement Computing Corporation...

Страница 2: ...al Harsh Environment Warranty and Measurement Computing Corporation are either trademarks or registered trademarks of Measurement Computing Corporation IBM PC and PC AT are trademarks of International...

Страница 3: ...rice I O boards face some tough operating conditions some more severe than the boards are designed to withstand When a board becomes damaged just return the unit with an order for its replacement at o...

Страница 4: ......

Страница 5: ...e 2 3 Installing the hardware 2 4 Configuring the hardware 2 5 Differential input mode 2 5 Single ended input mode 2 5 Non referenced single ended input mode 2 6 DAQ Sync configuration 2 6 Connecting...

Страница 6: ...l 4 24 CTR1 OUT signal 4 25 CTR2 CLK signal 4 25 CTR2 GATE signal 4 26 CTR2 OUT signal 4 26 Chapter 5 Calibrating the Board 5 1 Introduction 5 1 Calibration theory 5 1 Chapter 6 Specifications 6 1 Ana...

Страница 7: ...PCI DAS6052 User s Guide Environmental 6 13 Mechanical 6 13 DAQ Sync Connector and Pin Out 6 14 Main Connector and Pin Out 6 14 vii...

Страница 8: ......

Страница 9: ...t matter you are reading Caution Shaded caution statements present information to help you avoid injuring yourself and others damaging your hardware or losing your data Angle brackets that enclose num...

Страница 10: ...vailable on our web site at www mccdaq com registermaps RegMapSTC6000 pdf The Specifications PCI DAS6052 the PDF version of Chapter 6 in this guide is available on our web site at www mccdaq com pdfs...

Страница 11: ...at are available at a 100 pin I O connector Six pins are configurable as inputs and three are configurable as outputs Refer to Chapter 4 Functional Details and Chapter 6 Specifications for more inform...

Страница 12: ...uisition board and creates the board configuration file for use by your program or application software package The procedure for installing InstaCal is explained in the Software Installation Manual a...

Страница 13: ...oard make sure each of the items shown below is included Standard components The following items should be included with your shipment PCI DAS6052 InstaCal installation CD If you ordered the optional...

Страница 14: ...y of the following products with your board they should be included with your shipment Universal Library Universal Library Data Acquisition and Control Programming Tools also includes InstaCal install...

Страница 15: ...rself with a wrist grounding strap or by holding onto a grounded object such as the computer chassis Touch the antistatic container to the computer chassis before removing the board from the container...

Страница 16: ...displays as the system loads indicating that new hardware has been detected If the information file for this board is not already loaded onto your PC you are prompted for the disk containing this file...

Страница 17: ...surementcomputing com signals signals pdf Differential input mode When all channels are configured for differential input mode eight analog input channels are available In this mode the input signal i...

Страница 18: ...LLGND This mode is useful when the application calls for differential input mode but the limitation on channel count prevents it DAQ Sync configuration Multiple boards in the PCI DAS6000 series may b...

Страница 19: ...cables and compatible accessory boards that can be used with the PCI DAS6052 board Connector type Shielded SCSI 100 D Type C100HD50 x unshielded ribbon cable x 3 or 6 feet Compatible Cables C100MMS x...

Страница 20: ...A GND DIO1 86 36 D A OUT 0 DIO0 85 35 AISENSE n c 84 34 n c n c 83 33 n c n c 82 32 n c n c 81 31 n c n c 80 30 n c n c 79 29 n c n c 78 28 n c n c 77 27 n c n c 76 26 n c n c 75 25 n c n c 74 24 n c...

Страница 21: ...DIO3 88 38 D A OUT1 DIO2 87 37 D A GND DIO1 86 36 D A OUT 0 DIO0 85 35 AISENSE n c 84 34 n c n c 83 33 n c n c 82 32 n c n c 81 31 n c n c 80 30 n c n c 79 29 n c n c 78 28 n c n c 77 27 n c n c 76 26...

Страница 22: ...The red stripe identifies pin 1 The red stripe identifies pin 51 Strain relief is Stamped Pins 51 100 Figure 2 1 C100HD50 x Cable Connections Details on the C100HD50 x cable are available on our web s...

Страница 23: ...DS 14 3 cable Table 2 5 DAQ sync connector pinout view from top Signal Name Pin Pin Signal Name DS A D START TRIGGER 1 2 GND DS A D STOP TRIGGER 3 4 GND DS A D CONVERT 5 6 GND DS D A UPDATE 7 8 GND DS...

Страница 24: ...daq com cbicatalog cbiproduct asp dept_id 102 pf_id 281 SCB 50 50 conductor shielded signal connection screw terminal box provides two independent 50 pin connections Details on this product are availa...

Страница 25: ...ul user guide pdf Packaged applications programs Many packaged application programs such as SoftWIRE Labtech Notebook and HP VEE now have drivers for your board If the package you own does not have d...

Страница 26: ...e packaged application programs mentioned above to control your board Only experienced programmers should try register level programming If you need to program at the register level in your applicatio...

Страница 27: ...es A D and D A related data and commands There are three buffer memories provided on the memory bus The queue buffer 8K configuration memory stores programmed channel numbers gains and offsets The ADC...

Страница 28: ...tart of conversion SSH An active signal that terminates at the start of the last conversion in a scan A D STOP Indicates the end of a scan A D CONVERT ADC convert pulse default SCANCLK Delayed version...

Страница 29: ...START TRIGGER SYNC CLK Except for the SYNC CLK signal the DAQ Sync timing and control signals are a subset of the AUXIO signals available at the 100 pin I O connector These versions of the signals ar...

Страница 30: ...D A UPDATE D A START TRIGGER A D PACER GATE LOCAL BUS PCI BUS 5V 32 BIT 33 MHZ Boot EEPROM EXT CTR1 CLK CTR1 CLK USER COUNTER 2 Control 82C54 USER COUNTER 1 CTR2 GATE CTR1 GATE CTR2 OUT CTR1 OUT DIO 8...

Страница 31: ...r switching external multiplexers It is a 400 ns wide pulse that follows the CONVERT signal after a 50 ns delay This is adequate time for the analog input signal to be acquired so that the next signal...

Страница 32: ...TRIGGER source is programmable and may be set to any of the AUXIN inputs or to the DAQ Sync DS A D START TRIGGER input The polarity of this signal is also programmable to trigger acquisitions on eithe...

Страница 33: ...Counter Don t care The A D STOP TRIGGER signal signifies when the circular buffer should stop and when the specified number of post trigger samples should be acquired It is available as an output and...

Страница 34: ...A D STOP TRIGGER Output Signal Timing STARTSCAN signal The STARTSCAN output signal indicates when a scan of channels has been initiated You can program this signal to be available at any of the AUXOU...

Страница 35: ...CONVERT signal The A D CONVERT signal indicates the start of an A D conversion It is available through software selection as an input to any of the AUXIN pins defaulting to AUXIN0 or the DAQ Sync DS A...

Страница 36: ...he AUXIN pins If the A D PACER GATE signal is active no scans can occur If the A D PACER GATE signal becomes active during a scan in progress the current scan is completed and scans are then held off...

Страница 37: ...ASE Signal Timing A D STOP signal The A D STOP signal indicates a completed acquisition sequence You can program this signal to be available at any of the AUXOUT pins The A D STOP output signal is a 5...

Страница 38: ...at any time using InstaCal The input range on the ATRIG pin is always 10V 12 bit DACs are used to set the HI and LO levels for the threshold s The threshold resolution in this mode is 4 88mV per step...

Страница 39: ...ional Details Trigger Above The acquisition will begin when the ATRIG signal first goes above the THRESH_HI This mode is non retriggerable Thresh_HI 2 2 1 0 1 Trigger Acquired Data 2 2 1 0 1 Figure 4...

Страница 40: ...onal Details Trigger Below The acquisition will begin when ATRIG signal fist goes below the THRESH_LO level This mode is non retriggerable Thresh_LO 2 2 1 0 1 Trigger Acquired Data 2 2 1 0 1 Figure 4...

Страница 41: ...sition is enabled whenever ATRIG goes above the THRESH_HI level Acquisition is suspended whenever the ATRIG signal goes below the THRESH_HI level This is a level sensitive gating mode Trigger Result 2...

Страница 42: ...uisition is enabled whenever ATRIG goes below the THRESH_LO level Acquisition is suspended whenever the ATRIG signal goes above the THRESH_LO level This is a level sensitive gating mode Trigger Acquir...

Страница 43: ...er ATRIG goes above the THRESH_HI level Acquisition is suspended whenever the ATRIG signal goes below the THRESH_LO level The hysteresis level is set by THRESH_LO This is a level sensitive gating mode...

Страница 44: ...r ATRIG goes below the THRESH_LO level Acquisition is suspended whenever the ATRIG signal goes above the THRESH_HI level The hysteresis level is set by THRESH_HI This is a level sensitive gating mode...

Страница 45: ...d whenever ATRIG is below the THRESH_HI level and above the THRESH_LO level Acquisition is suspended whenever the ATRIG signal is outside of this region This is a level sensitive gating mode Thresh_HI...

Страница 46: ...r ATRIG is above the THRESH_HI level or below the THRESH_LO level Acquisition is suspended whenever the ATRIG signal is between the THRESH_HI and THRESH_LO levels This is a level sensitive gating mode...

Страница 47: ...ailable as an output on any AUXOUT pin When used as an input the D A START TRIGGER signal may be software selected as either a positive or negative edge trigger The selected edge of the D A START TRIG...

Страница 48: ...olarity is software selectable DAC outputs update within 100ns of the selected edge The D A CONVERT pulses should be no less than 100 s apart When used as an output the D A CONVERT signal may be used...

Страница 49: ...ity is programmable The maximum frequency for the D A EXTERNAL TIME BASE signal is 20 MHz The minimum pulse width is 23 ns high or low There is no minimum frequency specification Figure 4 27 Figure 4...

Страница 50: ...requency specified Figure 4 28 Figure 4 28 CTR1 CLK Signal Timing shows the timing requirements for the CTR1 CLK signal tw L tw H 15 ns minimum tw H tp 100 ns minimum tw L 25 ns minimum CTR1 GATE sign...

Страница 51: ...e timing requirements for the CTR1 OUT signal for counter mode 0 and mode 2 CTR1 CLK TC CTR1 OUT Mode 2 CTR1 OUT Mode 0 CTR2 CLK signal The CTR2 CLK signal can serve as the clock source for independen...

Страница 52: ...gnal Rising Edge Polarity tw tw 25 ns minimum Falling Edge Polarity CTR2 OUT signal This signal is present on the CTR2 OUT pin The CTR2 OUT signal is the output of one of the two user s counters in an...

Страница 53: ...oard is operating at optimum calibration values Calibration theory Analog inputs are calibrated for offset and gain Offset calibration for the analog inputs is performed directly on the input amplifie...

Страница 54: ...trim DAC is used to adjust the gain of the DAC A separate DAC is used to adjust offset on the final output amplifier The calibration circuits are duplicated for both analog outputs see Figure 5 2 Fig...

Страница 55: ...digital A D GATE A D Gate Sources External analog ATRIG input CH0 IN through CH15 IN External digital Programmable active high or active low level or edge A D gating modes External analog See Analog T...

Страница 56: ...nd 10 C of factory calibration temperature Calibrator test source high side tied to Channel 0 High and low side tied to Channel 0 Low Low level ground is tied to Channel 0 Low at the user connector Ta...

Страница 57: ...06 0 479 500mV 0 0371 52 1 56 2 5 0 0 0006 0 243 250mV 0 0421 28 6 32 8 3 0 0 0006 0 137 100mV 0 0471 14 4 22 4 2 1 0 0006 0 064 50mV 0 0471 9 7 19 9 1 9 0 0006 0 035 0 to 10V 0 0071 476 491 43 5 0 00...

Страница 58: ...6 250mV 39 2 3 9 100mV 27 7 2 8 50mV 25 3 2 5 0 to 10V 573 57 3 0 to 5V 286 28 6 0 to 2V 115 11 5 0 to 1V 66 3 6 6 0 to 500mV 48 2 3 9 0 to 200mV 27 7 2 8 0 to 100mV 25 3 2 5 1 Averaged measurements...

Страница 59: ...S max 3 S typ 2 5V 20 S typ 10 S max 5 S max 4 S max 3 S typ 1V 20 S typ 10 S max 5 S max 4 S max 3 S typ 500mV 20 S typ 15 S max 5 S max 4 S max 3 S typ 250mV 20 S typ 15 S max 8 S max 4 S max 3 S t...

Страница 60: ...V Range 105dB CMRR 60Hz 0 to 0 1V 0 05V Range 105dB Small signal bandwidth all ranges 480 kHz Input coupling DC 100 Gohm in parallel with 100pF in normal operation Input impedance 820 Ohm typ in power...

Страница 61: ...ector Samples are gathered at the maximum specified single channel sampling rate Specification applies to differential mode operation Table 6 5 Analog Input Noise Performance Range LSBrms Typical Coun...

Страница 62: ...ng DC Output impedance 0 1ohms max Power up and reset DACs cleared to 0 volts 20mV max Table 6 6 Analog Output Absolute Accuracy Range Absolute Accuracy 10V 4 6 LSB 0 to 10V 7 7 LSB Table 6 7 Absolute...

Страница 63: ...nal digital D A START TRIGGER External analog ATRIG input CH0 IN through CH15 IN DAC trigger sources Software triggered External digital Software configurable for rising or falling edge DAC triggering...

Страница 64: ...d warm up time 15 minutes Calibration Auto calibration calibration factors for each range stored on board in non volatile RAM DC Level 5 000V 1mV Actual measured values stored in EEPROM Tempco 0 6ppm...

Страница 65: ...rrupt is generated when DAC waveform circuitry is active DAC_DONE Interrupt is generated when a DAC sequence completes DAC_FIFO_1 4_EMPTY Interrupt is generated DAC FIFO is empty DAC Interrupt sources...

Страница 66: ...TARTSCAN A pulse indicating start of conversion SSH Active signal that terminates at the start of the last conversion in a scan A D STOP Indicates end of scan A D CONVERT ADC convert pulse SCANCLK Del...

Страница 67: ...ay be set DS A D START TRIGGER DS A D STOP TRIGGER DS A D CONVERT DS D A UPDATE DS D A START TRIGGER DAQ Sync Signals SYNC CLK Power Consumption 5V 1 25 A typical 1 5A max Does not include power consu...

Страница 68: ...A D CONVERT 6 GND 7 DS D A UPDATE 8 GND 9 DS D A START TRIGGER 10 GND 11 RESERVED 12 GND 13 SYNC CLK 14 GND Main Connector and Pin Out Connector type Shielded SCSI 100 D Type C100HD50 x unshielded rib...

Страница 69: ...70 n c 21 n c 71 n c 22 n c 72 n c 23 n c 73 n c 24 n c 74 n c 25 n c 75 n c 26 n c 76 n c 27 n c 77 n c 28 n c 78 n c 29 n c 79 n c 30 n c 80 n c 31 n c 81 n c 32 n c 82 n c 33 n c 83 n c 34 n c 84 n...

Страница 70: ...22 n c 72 n c 23 n c 73 n c 24 n c 74 n c 25 n c 75 n c 26 n c 76 n c 27 n c 77 n c 28 n c 78 n c 29 n c 79 n c 30 n c 80 n c 31 n c 81 n c 32 n c 82 n c 33 n c 83 n c 34 n c 84 n c 35 AISENSE 85 DIO0...

Страница 71: ...rements relating to electromagnetic compatibility EN 55022 Class B 1995 Radiated and conducted emission requirements for information technology equipment ENV 50204 1995 Radio frequency electromagnetic...

Страница 72: ...Measurement Computing Corporation 16 Commerce Boulevard Middleboro Massachusetts 02346 508 946 5100 Fax 508 946 9500 E mail info mccdaq com www mccdaq com...

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