*
Register is reset to default value upon CHGIN rising edge.
Table 12. IntMaskB Register (0x08)
Table 13. ILimCntl Register (0x09)
ADDRESS:
0x08
MODE:
Read/Write
BIT
7
6
5
4
3
2
1
0
NAME
—
SysB
LimIntM
VLimIntM
Thrm
Buck1IntM
Thrm
Buck2IntM
Thrm
LDO1IntM
Thrm
LDO2IntM
Thrm
LDO3IntM
SysBLimIntM
SysBLimIntM masks the SysBLimInt interrupt in the IntB register (0x06).
0 = Mask
1 = Not masked
VLimIntM
VLimIntM masks the VLimInt interrupt in the IntB register (0x06).
0 = Mask
1 = Not masked
ThrmBuck1
IntM
0 = Mask
1 = Not masked
ThrmBuck2
IntM
0 = Mask
1 = Not masked
ThrmLDO1
IntM
0 = Mask
1 = Not masked
ThrmLDO2
IntM
0 = Mask
1 = Not masked
ThrmLDO3
IntM
0 = Mask
1 = Not masked
ADDRESS:
0x09
MODE:
Read/Write* or Read-Only if Write-Protect Enabled (see Table 38)
BIT
7
6
5
4
3
2
1
0
NAME
SysMin[2:0]
—
—
—
ILimCntl [1:0]
SysMin[2:0]
SysMin sets System Voltage Minimum Threshold. When SYS drops to this level, the charger current is reduced.
000 = 3.6V
001 = 3.7V
010 = 3.8V
011 = 3.9V
100 = 4.0V
101 = 4.1V
110 = 4.2V
111 = 4.3V
ILim
Cntl[
1
:0]
CHGIN Custom Input Current Limit
(see Electrical Characteristics table for details)
00 = 0mA
01 = 1
00mA
10 =
500mA
11 = 10
00mA
MAX20335
PMIC with Ultra-Low I
Q
Voltage Regulators and
Battery Chargers for Small Lithium Ion Systems
www.maximintegrated.com
Maxim Integrated
│
48