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Connectors on Matrox Solios eV-CLBL and Matrox Solios eV-CLFL boards 97

Hardware signal name

MIL constant for

auxiliary signal

Digitizer device

number for

auxiliary signal

Description

P1_TTL_AUX_IO_1

M_AUX_IO9

M_DEV1

TTL auxiliary signal (input/output) for acquisition path 1,

which supports: timer output (M_TIMER1 on M_DEV1),

trigger input (trigger controller 1 on acq path 1), user input,

or user output (M_USER_BIT3).

2+,17-

P1_LVDS_AUX_OUT1

M_AUX_IO13

M_DEV1

LVDS auxiliary signal (output) for acquisition path 1, which

supports: timer output (M_TIMER2 on M_DEV1) or user

output (M_USER_BIT1).

P1_LVDS_HSYNC_OUT-

HSYNC output for acq. path 1 (negative).

See pin 6 for more information.

P1_LVDS_HS

HSYNC output for acq. path 1 (positive).

P1_LVDS_

Clock output for acq. path 1 (positive).

Not connected.

P0_LVDS_

Clock output for acq. path 0 (positive).

12+,28- LVDS_AUX_IN1

M_AUX_IO5

M_DEV0/M_DEV1 LVDS auxiliary signal (input), shared between both

acquisition paths for trigger input (trigger controller 3 on

acq path 0; 3 or 1 on acq path 1) or user input, and

dedicated to acquisition path 1 for timer clock input or

quadrature input bit 1.

P0_TTL_AUX_IO_1

M_AUX_IO9

M_DEV0

TTL auxiliary signal (input/output) for acquisition path 0,

which supports: timer output (M_TIMER1/M_TIMER4 on

M_DEV0), trigger input (trigger controller 1 on acq path 0),

user input, or user output (M_USER_BIT3).

GND

Ground.

TTL_AUX_IO_1

M_AUX_IO3

M_DEV0/M_DEV1 TTL auxiliary signal (input/output), shared between both

acquisition paths for trigger input (trigger controller 3 on

acq path 0; 3 on acq path 1), user input, or user output

(M_USER_BIT5), and dedicated to acquisition path 1 for

timer output (M_TIMER2 on M _DEV1).

GND

Ground.

19+,3-

P0_LVDS_AUX_OUT1

M_AUX_IO13

M_DEV0

LVDS auxiliary signal (output) for acquisition path 0, which

supports: timer output (M_TIMER2 on M_DEV0) or user

output (M_USER_BIT1).

20+,4-

P0_LVDS_AUX_OUT0

M_AUX_IO12

M_DEV0

LVDS auxiliary signal (output) for acquisition path 0, which

supports: timer output (M_TIMER1 on M_DEV0) or user

output (M_USER_BIT0).

P1_LVDS_VSYNC_OUT-

VSYNC output for acq. path 1 (negative).

See pin 36 for more information.

Содержание Solios eV-CL

Страница 1: ...Matrox Solios eV Installation and Hardware Reference Manual no Y11113 101 0300 January 15 2014...

Страница 2: ...technical support including without limitation damages or costs relating to the loss of profits business goodwill even if advised of the possibility of such damages In no event will Matrox and its sup...

Страница 3: ...able separately 20 Handling components 20 Installation 21 Chapter 2 Hardware installation 23 Installing your Matrox Solios eV CL board 24 Installing the cable adapter bracket 27 Connecting video sourc...

Страница 4: ...47 Lookup tables 47 Communication 48 UARTs 48 PSGs 49 Camera control and auxiliary signals 49 Specifications of the auxiliary signals and camera control signals 56 Acquisition controller 62 Video for...

Страница 5: ...y I O connector 0 on the DBHD 44 DB 9 cable adapter bracket 95 External auxiliary I O connector 1 on the DBHD 44 DB 9 cable adapter bracket 99 External auxiliary I O connector 0 on the dual DBHD 15 ca...

Страница 6: ...Industry Canada Compliance Statement EU Notice European Union Directive on Waste Electrical and Electronic Equipment WEEE Product support Limited Warranty...

Страница 7: ...Chapter 1 Chapter 1 Introduction This chapter briefly describes the features of the Matrox Solios eV CL boards as well as the software that can be used with the boards...

Страница 8: ...llow all on screen instructions Once changed you must restart your computer perform a cold boot for changes to take effect The PCIe single Medium single Full board is capable of operating in either co...

Страница 9: ...I Os 3 LVDS transceivers OptoAux 2 TTL buffers Aux In 2 Aux Out 1 Optocoupler Aux I Os 3 ChannelLink Receiver 2 Clock Data 24 Syncs 4 24 LUTs LUTs 32 32 Cam Ctrl 4 Cam Ctrl 4 LVDS drivers LVDS drivers...

Страница 10: ...LUTs LUTs 32 32 Cam Ctrl 4 Cam Ctrl 4 LVDS drivers LVDS drivers LVDS driver receiver LVDS driver receiver 32 DDR2 up to 1 73 GB s 64 up to 860 MB s PCI X to PCIe Bridge Host PCIe bus Demultiplexer Dem...

Страница 11: ...I O connector 1 DBHD 15 or DB 9 LVDS transceivers OptoAux 2 TTL buffers Aux In 2 Optocoupler Aux I Os 1 Cam Ctrl 4 LVDS drivers LVDS driver receiver LUTs 64 64 up to 860 MB s PCI X to PCIe Bridge Hos...

Страница 12: ...Data 24 Syncs 4 24 Cam Ctrl 4 LVDS drivers LVDS driver receiver 32 DDR2 up to 1 73 GB s 64 up to 860 MB s PCI X to PCIe Bridge Host PCIe bus LUTs 64 Demultiplexer Matrox Solios eV CLBL single Medium...

Страница 13: ...26 24 UART LVDS transceivers OptoAux 2 External Auxiliary I O connector 0 DBHD 15 TTL buffers Aux In 2 Aux Out 1 Optocoupler Aux I Os 3 External Auxiliary I O connector 1 DBHD 15 or DB 9 LVDS transcei...

Страница 14: ...iver 32 DDR2 up to 1 73 GB s 64 up to 860 MB s PCI X to PCIe Bridge Host PCIe bus LUTs 64 Demultiplexer Matrox Solios eV CLFL Acquisition memory 128 256 512 MB 28 bits serialized across 4 LVDS pairs I...

Страница 15: ...16 MHz DDR2 SDRAM to store acquisition data This memory is referred to as acquisition memory Additional functionality In addition to the core video capture capabilities Matrox Solios eV CL incorporate...

Страница 16: ...he Host at a peak transfer rate of up to 1 Gbyte sec the maximum achievable bandwidth depends on the type of camera and digitizer configuration format DCF used Optimum conditions include using the boa...

Страница 17: ...bead inspection continuous strip of material 3D reconstruction and color analysis MIL applications are easily ported to new Matrox hardware platforms and can be designed to take advantage of multi pro...

Страница 18: ...re IA32 or equivalent A relatively up to date PCIe chipset The list of platforms that are known to be compatible with Matrox Solios eV CL are available on the Matrox website under the board s PC compa...

Страница 19: ...which was purchased Depending on the board purchased you will receive a different alternative cable adapter bracket to access the signals of the internal auxiliary I O connectors from outside the com...

Страница 20: ...the original Matrox Solios eCL XCL board Note however when using the DB 9 connector some DBHD 15 signals are not available If needed you can purchase a Camera Link or PoCL compliant Camera Link cable...

Страница 21: ...akes reference to a MIL Lite function However anything that can be accomplished with MIL Lite can also be accomplished with MIL or Matrox Inspector Need help If you experience problems during installa...

Страница 22: ...22 Chapter 1 Introduction...

Страница 23: ...Chapter 2 Chapter 2 Hardware installation This chapter explains how to install your Matrox Solios eV CL board in your computer...

Страница 24: ...city from your body by touching a metal part of the computer chassis Proceed with the following stepsto install your board Note that your board should be installed before you install your software 1 R...

Страница 25: ...move it Keep the screw from the top of the plates to anchor your boards once they are installed 4 Position your Matrox Solios eV CL board in the selected slot and then press the board firmly but caref...

Страница 26: ...Video Device and you will be asked to assign it a driver At this point you should click on Cancel Under Windows and Linux the driver will be installed during the installation of Matrox Solios eV CL s...

Страница 27: ...L board To attach the flat ribbon cable position the cable so that the red wire is on the same side as the bracket of the Matrox Solios eV CL board With the Matrox Solios eV CL board and the cable in...

Страница 28: ...the flat ribbon cable of the DB 9 connector to the internal auxiliary 10 pin connector If you have two DBHD 15 connectors on your cable adapter bracket you should attach the flat ribbon cables of the...

Страница 29: ...n the video source and the frame grabber External auxiliary I O connector 0 DBHD 15 Used to transmit receive auxiliary signals for one of the acquisition paths By default it carries the auxiliary sign...

Страница 30: ...single Medium video source to a board operating in dual Base configuration could seriously damage your video source Note that for Matrox Solios eV CLB the board is factory configured to operate in sin...

Страница 31: ...d synchronization signals and transmit receive auxiliary signals The connector is located on the edge of the board making the signals accessible from inside the computer enclosure Matrox Solios eV CLB...

Страница 32: ...Link connector MDR at one end For Matrox Solios eV CLBL you should use PoCL compliant Camera Link cables MDR when connecting to PoCL compliant video sources Camera Link cables are not available from...

Страница 33: ...Chapter 3 Chapter 3 Using multiple Matrox Solios eV CL boards This chapter explains how to use multiple Matrox Solios eV CL boards...

Страница 34: ...multaneously capture images from video sources attached to different Matrox Solios eV CL boards however the number of video sources from which you can simultaneously capture images is computer depende...

Страница 35: ...Chapter 4 Chapter 4 Matrox Solios eV CL hardware reference This chapter explains the architecture features and modes of the Matrox Solios eV CL hardware...

Страница 36: ...o grab from one input source of the specified type When several MIL digitizers are allocated their device number along with their DCF identify if they represent the same path s but perhaps for a diffe...

Страница 37: ...r space converter of the video formatter grabbed data can be converted to RGB24 RGB32 or YUV16 format In addition data can be converted to 8 bit 10 bit 12 bit 14 bit and 16 bit monochrome data Matrox...

Страница 38: ...up to 32 bits when acquiring from non standard time multiplexed video sources Similarly a Medium type acquisition path can grab up to 48 bits of video data when acquiring from Camera Link compliant so...

Страница 39: ...RT LVDS transceivers OptoAux 2 External Auxiliary I O connector 0 DBHD 15 External Auxiliary I O connector 1 DBHD 15 or DB 9 TTL buffers Aux In 2 Aux Out 1 Optocoupler Aux I Os 3 LVDS transceivers Opt...

Страница 40: ...Clock Out 2 Optocoupler Aux I Os 6 ChannelLink Receiver 2 Clock Data 24 Syncs 4 24 LUTs LUTs 32 32 Cam Ctrl 4 Cam Ctrl 4 LVDS drivers LVDS drivers LVDS driver receiver LVDS driver receiver Demultiple...

Страница 41: ...ux Out 1 Optocoupler Aux I Os 3 External Auxiliary I O connector 1 DBHD 15 or DB 9 LVDS transceivers OptoAux 2 TTL buffers Aux In 2 Optocoupler Aux I Os 1 Cam Ctrl 4 LVDS drivers LVDS driver receiver...

Страница 42: ...C Out 1 VSYNC Out 1 Clock Out 1 Optocoupler Aux I Os 4 ChannelLink Receiver 2 Clock Data 24 Syncs 4 24 Cam Ctrl 4 LVDS drivers LVDS driver receiver LUTs 64 Demultiplexer Acquisition section of Matrox...

Страница 43: ...1 DBHD 15 or DB 9 LVDS transceivers OptoAux 2 TTL buffers Aux In 2 Optocoupler Aux I Os 1 Cam Ctrl 4 LVDS drivers LVDS driver receiver LUTs 64 ChannelLink Receiver 2 Clock Data 28 28 ChannelLink Recei...

Страница 44: ...lLink Receiver 2 Clock 28 Cam Ctrl 4 LVDS drivers LVDS driver receiver LUTs 64 Demultiplexer Acquisition section of Matrox Solios eV CLFL 28 bits serialized across 4 LVDS pairs In single Medium mode C...

Страница 45: ...ber of non sequential memory regions see the Acquisition controller section later in this chapter Video sources supported per acquisition path Camera Link Standard One tap x 8 10 12 14 16 bit Two tap...

Страница 46: ...chronously in single Medium configuration they only use two of the receivers whereas in single Full configuration they use all three receivers For Matrox Solios eV CLB and eV CLBL each ChannelLink rec...

Страница 47: ...n only deserialize video inputs that when combined and if necessary expanded total a maximum depth of 64 bits per acquisition path Expansion refers to the automatic addition of padding zeros on the mo...

Страница 48: ...communication between the video source and the board These signals are handled by the Universal Asynchronous Receiver Transmitters UARTs For each acquisition path four camera control output signals a...

Страница 49: ...which is user defined the table in the next subsection identifies the functions to which the camera control and auxiliary signals can be defined The PSGs are also responsible for implementing the func...

Страница 50: ..._ I N 0 L V D S _ A U X _ I N 1 P 0 _ L V D S _ A U X _ O U T 0 P 1 _ L V D S _ A U X _ O U T 0 Timer M_TIMERx 0 1 2 1 2 1 2 1 2 3 1 4 2 1 1 1 2 1 2 1 2 1 2 3 1 4 2 1 Trigger controller affected by i...

Страница 51: ...0 0 0 1 1 1 1 0 0 0 1 1 1 0 1 0 1 Auxiliary input signal or auxiliary I O signal set to input M _ A U X _ I O x A c q u i s i t i o n P a t h C C 1 C C 2 C C 3 C C 4 C C 1 C C 2 C C 3 C C 4 P 0 _ T T...

Страница 52: ...C C 4 P 0 _ T T L _ A U X _ I O _ 0 P 0 _ T T L _ A U X _ I O _ 1 P 1 _ T T L _ A U X _ I O _ 0 P 1 _ T T L _ A U X _ I O _ 1 T T L _ A U X _ I O _ 0 T T L _ A U X _ I O _ 1 P 0 _ O P T O _ A U X _ I...

Страница 53: ...T T L _ A U X _ I O _ 1 P 0 _ O P T O _ A U X _ I N 0 P 0 _ O P T O _ A U X _ I N 1 O P T O _ A U X _ I N 0 O P T O _ A U X _ I N 1 P 0 _ L V D S _ A U X _ I N 0 P 0 _ L V D S _ A U X _ I N 1 L V D S...

Страница 54: ...to access this signal x 8 9 2 8 9 3 12 13 12 13 y 1 2 3 4 1 2 3 4 z 0 0 0 0 1 1 1 1 0 0 0 1 1 1 0 1 0 0 1 1 Auxiliary input signal orauxiliaryI O signal set to input M _ A U X _ I O x A c q u i s i t...

Страница 55: ...VDS_VSYNC_OUT Line valid input 0 0 1 0 HSYNC output 0 0 0 0 0 P0_LVDS_HSYNC_OUT 1 0 0 0 0 P1_LVDS_HSYNC_OUT Data valid input 0 0 1 0 Clock input 0 Xclk CL connect 0 1 Xclk CL connect 1 Clock output 0...

Страница 56: ...positive and negative components of the signal must be between 4 06 V and 9 165 V for logic high and between 5 0 V and 0 8V for logic low Auxiliary signals per path total This is the number of auxilia...

Страница 57: ...o 65535 clock ticks before resetting The timers can use one of the following as a clock source A clock that is internally generated Each timer can use its PSG s clock generator which can generate a si...

Страница 58: ...than two pixels if using the trigger to start a timer the trigger signal s pulse width must be greater than two clock periods of the timer To determine the timer As of MIL 10 PSG 0 PSG 1 P0_TTL_AUX_IO...

Страница 59: ...synchronization signal to the video source Through the Camera Link connectors the board also receives synchronization data frame valid line valid and data valid along with the video data refer to the...

Страница 60: ...sequence 00 10 11 01 or 00 01 11 10 respectively Upon decoding a Gray code the rotary decoder increments or decrements its 32 bit internal counter depending on the direction of movement You can config...

Страница 61: ...to as a user bit Your application can also act upon and interpret the state of an auxiliary input signal or I O signal set to input The state of an auxiliary input signal is not associated with a use...

Страница 62: ...the acquisition controller can write to eight non sequential memory regions per acquisition path regardless of the configuration To establish the number of non sequential memory regions to which your...

Страница 63: ...hereas there isno restriction in the vertical direction subsampling occurs using nearest neighbor interpolation Flipping Image data can be flipped vertically Bayer color decoding only on Matrox Solios...

Страница 64: ...atically converts the bit depth and color format of the source image to the bit depth and color format of the destination buffer The DCF establishes the source image data while the destination grab bu...

Страница 65: ...o communicate with the Host Matrox Solios eV CL transfers data using the Host s PCIe bus The PCI X to PCIe bridge handles the protocol conversion Under optimum conditions Matrox Solios eV CL can excha...

Страница 66: ...66 Chapter 4 Matrox Solios eV CL hardware reference...

Страница 67: ...Appendix A Appendix A Glossary This appendix defines some of the specialized terms used in the Matrox Solios eV CL documentation...

Страница 68: ...known as the horizontal blanking period The portion of a video signal after the end of a frame and before the beginning of a new frame is known as the vertical blanking period Contiguous memory A bloc...

Страница 69: ...f the two halves that together make up the image grabbed from an interlaced video source One half consists of the image s odd lines known as the odd field the other half consists of the image s even l...

Страница 70: ...s the end of a line and the start of a new one See also vertical synchronization signal Interlaced scanning Describes a transfer of data in which the odd numbered lines of the source are written to th...

Страница 71: ...lso known as live processing Rotary encoder A device used to convert the angular position of a shaft or axle to an analog or digital code Saturate To replace overflows or underflows in an operation wi...

Страница 72: ...f a frame and before the beginning of a new frame During this period the video signal is blank See also horizontal blanking period Vertical synchronization signal The part of a video signal that indic...

Страница 73: ...Appendix B Appendix B Technical information This appendix contains information that might be useful when installing your Matrox Solios eV CL board...

Страница 74: ...list of platforms that are known to be compatible with Matrox Solios eV CL are available on the Matrox website under the board s PC compatibility list A proper power supply Refer to the Electrical spe...

Страница 75: ...c cable Supports frame and line scan video sources The min max length for an image and min max width for a line are as follows Can convert captured data to RGB24 RGB32 or YUV16 format In addition data...

Страница 76: ...specific auxiliary input signals or HSYNC output VSYNC output clock output timer output or user output per acquisition path Three TTL auxiliary I O signals trigger input field polarity input user inpu...

Страница 77: ...bit LUTs 1 palette of one or two 4096 entry 8 or 16 bit LUTs Instead of being mapped through a LUT 14 and 16 bit data by pass the LUTs Features specific to Matrox Solios eV CLB and eV CLBL in single M...

Страница 78: ...output per acquisition path Features specific to Matrox Solios eV CLBL and Matrox Solios eV CLFL Separate LVDS pixel clock output HSYNC output and VSYNC output signals per acquisition path Two additi...

Страница 79: ...common mode 1 125 V min to 1 375 V max low 1 02 V typ 0 9 V min high 1 33 V typ 1 6 V max Input signals in TTL format No termination Pulled up to 3 3 V with 4 716 kOhm Clamped to 0 7 V and to 5 7 V In...

Страница 80: ...L x 11 12 H x 1 56 W cm 6 6 x 4 376 x 0 613 from bottom edge of goldfinger to top edge of board Ventilation 100 LFM between boards Minimum maximum ambient operating temperature 0 C to55 C 32 F to 131...

Страница 81: ...O connector In addition close to the top edge of the boards there are two internal auxiliary I O connectors Auxiliary I O Connector 0 Camera Link Video Input Connector 0 Camera Link Video Input Connec...

Страница 82: ...UX_IN0 P0_OPTO_AUX_IN1 P0_LVDS_AUX_IN0 and P0_LVDS_AUX_IN1 Notice that the ranking of the LVDS signals also starts at 0 Camera Link video input connectors On Matrox Solios eV CLB and Matrox Solios eV...

Страница 83: ...4 Inner shield Ground 15 2 CC4 M_CC_IO4 Camera control output 4 for acquisition path 0 which supports timer output M_TIMER1 M_TIMER2 on M_DEV0 user output M_USER_BIT_CC_IO0 M_USER_BIT_CC_IO1 on M_DEV0...

Страница 84: ...rent propagation delays Pin Hardware signal name MIL constant for auxiliary signal Description 1 GND or PWR_OUT Ground inner shield or 12V to camera in PoCL mode 2 15 Z3 Video input data Z3 3 16 Zclk...

Страница 85: ...V CLB and Matrox SolioseV CLF is not compatible with display devices Connecting the DBHD 15 connector on Matrox Solios eV CLB or Matrox Solios eV CLF to a VGA monitor or any other display device might...

Страница 86: ...ut trigger controller 0 on acq path 0 user input field polarity input or quadrature input bit 0 6 8 P0_LVDS_AUX_IN1 M_AUX_IO11 M_DEV0 LVDS auxiliary signal input for acquisition path 0 which supports...

Страница 87: ...87 To build your own cable you can purchase the following parts These parts can be purchased from third parties such as Digi Key Corporation www digikey com Mating information Manufacturer NorComp Inc...

Страница 88: ...display device might damage both the device and the board The pinout for the auxiliary I O connector is as follows TC stands for trigger controller andacq path standsfor acquisitionpath Ifthe auxilia...

Страница 89: ...path 1 for field polarity input or quadrature input bit 0 6 8 LVDS_AUX_IN1 M_AUX_IO5 M_DEV0 M_DEV1 LVDS auxiliary signal input shared between both acquisition paths for trigger input trigger controll...

Страница 90: ...gnals for one of the acquisition paths By default the auxiliary I O connectors carry the auxiliary signals for acquisition path 1 if a jumper is installed on the 2 pin I O acquisition path connector t...

Страница 91: ...ignal name MIL constant for auxiliary signal Digitizer device for auxiliary signal 2 1 6 5 LVDS_AUX_IN0 M_AUX_IO4 M_DEV0 M_DEV1 PO_LVDS_AUX_IN0 M_AUX_IO10 M_DEV0 3 6 4 3 OPTO_AUX_IN0 M_AUX_IO0 M_DEV0...

Страница 92: ...iary I O connector 1 swap their pinout description Jumper Description Not installed default Auxiliary I O connector 0 has the pinout description which includes P0_ signals Auxiliary I O connector 1 ha...

Страница 93: ...eceived there is either a 44 pin and 10 pin set of internal auxiliary I O connectors for use with the DBHD 44 DB 9 external auxiliary I O connectors or there is a 32 pin internalauxiliary I O connecto...

Страница 94: ...ranking that reflects the number of signals of that type format and direction for a path For example two TTL and two LVDS auxiliary input signals for path 0 would be named P0_TTL_AUX_IN0 P0_TTL_AUX_IN...

Страница 95: ...out of the corresponding connectors on Matrox Solios eV CLB and Matrox Solios eV CLF described earlier in this appendix To interface with the above connectors use a standard Camera Link cable with a 2...

Страница 96: ...tor It is used to transmit timing and synchronization signals and transmit receive auxiliary signals It interfaces with the 44 pin internal auxiliary I O connector on the board making the I O signals...

Страница 97: ...cquisition paths for trigger input trigger controller 3 on acq path 0 3 or 1 on acq path 1 or user input and dedicated to acquisition path 1 for timer clock input or quadrature input bit 1 13 P0_TTL_A...

Страница 98: ...drature input bit 0 33 18 P1_LVDS_AUX_OUT0 M_AUX_IO12 M_DEV1 LVDS auxiliary signal output for acquisition path1 which supports timer output M_TIMER1 on M_DEV1 or user output M_USER_BIT0 34 GND Ground...

Страница 99: ...4 and dedicated to acquisition path 0 for timer output M_TIMER2 on M_DEV0 44 NC Not connected These MIL constants represent the signals as of MIL 10 The signals that were previously represented by M_H...

Страница 100: ...supports timer output M_TIMER3 on M_DEV0 trigger input trigger controller 0 on acq path 0 user input user output M_USER_BIT2 or field polarity input 4 5 P0_OPTO_AUX_IN1 M_AUX_IO7 Opto isolated auxili...

Страница 101: ...connector 0 on the Matrox Solios eV CLBL and Matrox Solios eV CLFL dual DBHD 15 cable adapter bracket is not compatible with display devices Connecting the DBHD 15 connector on the cable adapter brack...

Страница 102: ...LBL and Matrox Solios eV CLFL dual DBHD 15 cable adapter bracket is not compatible with display devices Connecting the DBHD 15 connector on the cable adapter bracket to a VGA monitor or any other disp...

Страница 103: ...ds 103 To build your own cable you can purchase the following parts These parts can be purchased from third parties such as Digi Key Corporation www digikey com Mating information for DB 15 Manufactur...

Страница 104: ...respectively You can use the connectors to transmit receive auxiliary signals for the two acquisition paths The connectors are located close to the top edge of the board making the auxiliary signals a...

Страница 105: ...und 14 10 P0_LVDS_AUX_OUT0 M_AUX_IO12 M_DEV0 LVDS auxiliary signal output for acquisition path 0 which supports timer output M_TIMER1 on M_DEV0 or user output M_USER_BIT0 15 P1_TTL_AUX_IO_0 M_AUX_IO8...

Страница 106: ...acq path 0 user input or user output M_USER_BIT3 39 TTL_AUX_IO_0 M_AUX_IO2 M_DEV0 M_DEV1 TTL auxiliary signal input output shared between both acquisition paths for trigger input trigger controller 2...

Страница 107: ...user input or field polarity input 6 5 P0_LVDS_AUX_IN0 M_AUX_IO10 M_DEV0 LVDS auxiliary signal input foracquisition path0 which supports trigger input trigger controller 0 on acq path 0 user input fie...

Страница 108: ...LFL board is a 0 1 spacing 32 pin male connector This connector is to be connected to the dual DBHD 15 connector s flat ribbon cable You can use the connector to transmit receive auxiliary signals for...

Страница 109: ...1 on M_DEV0 or user output M_USER_BIT0 10 9 P0_LVDS_AUX_IN1 M_AUX_IO11 M_DEV0 LVDS auxiliary signal input for acquisition path 0 which supports trigger input trigger controller 1 on acq path 0 user in...

Страница 110: ...clock input or quadrature input bit 1 27 P1_TTL_AUX_IO_1 M_AUX_IO9 M_DEV1 TTL auxiliary signal input output for acquisition path 1 which supports timer output M_TIMER1 on M_DEV1 trigger input trigger...

Страница 111: ...Appendix C Appendix C Acknowledgments This appendix lists the copyright information regarding third party material used to implement components on the Matrox Solios eV CL board...

Страница 112: ...Neither the name of the author nor the names of other contributors may be used to endorse or promote products derived from this software without specific prior written permission THIS SOFTWARE IS PROV...

Страница 113: ...Appendix D Appendix D Major revisions of Matrox Solios eV CL boards This appendix lists the major revisions of the Matrox Solios eV CL boards...

Страница 114: ...revisions of Matrox Solios eV CL boards Major revisions of Matrox Solios eV CL Versions of Matrox Solios eV CL Part number Version Description SOL2MEVCLB 006 First shipping version SOL2MEVCLF 006 Fir...

Страница 115: ...nector 1 88 99 internal auxiliary I O 90 103 107 internal I O acquisition path connector 91 D data transfer 16 65 DCF defined 68 see digitizer configuration format digitizer configuration format 36 di...

Страница 116: ...slot 18 24 pixel clock Matrox Solios eV CL 59 Programmable Synchronization Generators 49 Q quadrature input 60 Gray code 60 R requirements computer 18 RGB 15 37 45 rotary decoder 60 RS 232 compatible...

Страница 117: ...in accordance with the instruction manual may cause harmful interference to radio communications Operation of these devices in a residential area is likely to cause harmful interference in which case...

Страница 118: ...lectrical and Electronic Equipment WEEE Europe English European user s information Directive on Waste Electrical and Electronic Equipment WEEE Please refer to the Matrox Web site www matrox com enviro...

Страница 119: ...Limited Warranty Refer to the warranty statement that came with your product...

Страница 120: ......

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