Matrox Solios eA, Установка и справочник по оборудованию, Страница: 84 / 196

84 Chapter 4: Matrox Solios hardware reference
Next valid frame/field and asynchronous reset modes
Each PSG can operate in two modes: next valid frame/field mode and
asynchronous reset mode. In next valid frame/field mode, the board waits for the
next valid frame or field (as specified by the DCF file) before commencing the grab.
In asynchronous reset mode, the board resets the video source to begin a new frame
when the trigger signal is received. The board uses an exposure timer signal to reset
the video source.
Trigger signals
When in either next valid frame/field mode or in asynchronous reset mode, the
board accepts trigger input signals, which allow acquisition to be synchronized
with external events. Each PSG accepts two external trigger input signals: one
TTL or LVTTL trigger input and another trigger input that passes through an
opto-coupler, a device that protects the board from outside surges. For each PSG,
you can also program two path-independent auxiliary signals as trigger input
signals; these can be received in LVDS, TTL, or LVTTL.
When received in TTL format directly, the signal must have a maximum
amplitude of 5 V; when received in LVTTL format directly, the signal must have
a maximum amplitude of 3.3 V. A signal over 2 V is considered high, while
anything less than 0.8 V is considered low; the transition of 0.8 V to 2 V is
considered to be the rising edge.
If using the trigger to start acquisition, the trigger signal’s pulse width must be
greater than two pixels; if using the trigger to start the exposure timer, the trigger
signal’s pulse width must be greater than two clock periods of the timer. To
determine the timer period, take the inverse of the pixel or timer’s clock frequency,
respectively. For example, if the pixel frequency is 12.27 MHz, the minimum pulse
width is 2 x 1/12.27 MHz (approximately 163 nsec).
A trigger signal connected to external I/O connector 1 of the adapter board, passes
through an opto-coupler. The voltage difference across the positive and negative
components of the signal must be between 3.15 V and 6.45 V for logic high, and
between -5.0 V and 0.8 V for logic low.