40
QH21: SiI 504
SiI 504
HostAddr7
157
158
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6
RSVD
VDDCore GNDCore
LCDPwrEn
/CBlank /CSync
/VSync /HSync
Blue_Cb0 Blue_Cb1 Blue_Cb2 Blue_Cb3 Blue_Cb4 Blue_Cb5
GNDIO
VDDIO
Blue_Cb6 Blue_Cb7 Blue_Cb8 Blue_Cb9
GNDIO
Green_Y0 Green_Y1 Green_Y2 Green_Y3
VDDIO
Green_Y4 Green_Y5 Green_Y6 Green_Y7 Green_Y8 Green_Y9
GNDIO
Red_Cr0
Red_Cr1 Red_Cr2 Red_Cr3 Red_Cr4 Red_Cr5 GNDCore VDDCore Red_Cr6 Red_Cr7 Red_Cr8 Red_Cr9 VidOutClk GNDCore
/BypPLLClk48M
Clk48M
GNDCore
VDDCore /ExtRefSel
RSVD
GNDCore
MemClk
GNDCore
VDDCore
MemData14
MemData13
MemData12
MemData11
MemData10
GNDIO
MemData9
MemData8
PuPdDis
VDDIO
MemData0
MemData1
MemData2
GNDIO
MemData3
MemData4
MemData5
MemData6
MemData7
GNDIO
DQM
/WE
/CAS
/RAS
VDDIO
VDDIO
GNDIO
RSVD
MemAddr11
MemAddr10
MemAddr9
GNDIO
MemAddr8
MemAddr7
MemAddr6
GNDIO
MemAddr5
MemAddr4
MemAddr0
MemAddr1
MemAddr2
MemAddr3
VDDCore
GNDCore
RSVD
RSVD
HostAddr5 HostAddr4 HostAddr3 HostAddr2 HostAddr1 HostAddr0 GNDCore
/HostCS /HostRd_SDA /HostWr_SCL VDDCore VidInClk GNDIO VidInData9 VidInData8 VidInData7 VidInData6 VidInData5 VidInData4 VidInData3 VidInData2 VDDIO ExtRefXtalOut ExtRefXtalIn VDDIO GNDIO MemData16 MemData17 MemData18 MemData19 GNDIO MemData20 MemData21 MemData22 MemData23 GNDIO MemData31 MemData30 GNDIO VDDIO MemData29 MemData28 GNDIO MemData27 MemData26 MemData25 MemData24 MemData15 /BypPLLMemCl
k
GNDCore
VDDCore
RSVD
HostAddr6
HostMode
VDDCore
HostClk
HostData15\VidInData19
GNDcore
HostData14\VidInData18
HostData13\VidInData17
HostData12\VidInData16
VDDCore
GNDCore
HostData11\VidInData15
HostData10\VidInData14
HostData9\VidInData13
RSVD
HostData8\VidInData12
HostData7\VS
HostData6\HS
HostData5
HostData3
HostData4
HostData2
HostData1
HostData0
GNDIO
VDDIO
/Det32PD
/Det22PD
/DetVideo
MemAddr12
/DeintDone
VDDIO
GNDIO
SDOut
SCKOut
VDDIO
SDIn
WSIn
GNDIO
SCKIn
VDDCore
/Reset
Test0
/BypPLLClk54_72M
Test1
Clk54_72M
VDDCore
GNDCore
AVDD
ARTN
WSOut
RSVD
Signal Group
Signal Name
Notes Type
Description
Video Input
VidInData[9:2]
5V
In
Multiplexed Video Input Data (ITU-R BT.656,
8-bit & H/V syncs formats); Y (luma) Video
Input Data (16-bit & H/V syncs format).
VidInData[19:12]
5V/PD
In
Chroma Video Input Data (16-bit & H/V syncs
(HostData[15:8])
format only). See Host Interface pin list for
pin functions when not used for video input.
VS
5V/PD
In
Vertical Sync input (8/16-bit & H/V syncs
(HostData[7])
format only). See Host Interface pin list for
pin function when not used for video input.
HS
5V/PD
In
Horizontal Sync input (8/16-bit & H/V syncs
(HostData[6])
format only). See Host Interface pin list for
pin function when not used for video input.
VidInClk
5V
In
Video Input Clock, 27.0 MHz
Video Output
Red_Cr[9:0]
Out
Red Data (RGB output mode);
Cr Data (YCrCb output mode)
Green_Y[9:0]
Out
Green Data (RGB output mode);
Y Data (YCrCb output mode)
Blue_Cb[9:0]
Out
Blue Data (RGB output mode);
Cb Data (YCrCb output mode)
/HSync
Out
Horizontal Sync
/VSync
Out
Vertical Sync
/CSync
Out
Composite Sync
/CBlank
Out
Composite Blank
LCDPwrEn
Out
LCD Power Enable
VidOutClk
Out
Video Output Clock, 36, 27 or 24 MHz
Clk48M
5V
InOut
48 MHz Clock. Normally, this pin is a no-
connect, outputting an internal PLL-generated
48.0 MHz clock and receiving that same clock
through its input buffer. To bypass the PLL,
set /BypPLLClk48M = 0, and supply a 48.0
MHz clock to the Clk48M pin.
Signal Group
Signal Name
Notes Type
Description
Memory
/RAS
Out
SDRAM Row Address Strobe.
/CAS
Out
SDRAM Column Address Strobe.
/WE
Out
SDRAM Write Enable.
DQM
Out
SDRAM Data Mask.
MemData[31:0]
5V
InOut
SDRAM Data.
MemAddr[12:0]
5V/PU/PD InOut
SDRAM Address when an output.
Configuration at reset when and input.
See Memory Subsystem an Hardware
Configuration sections of Functional
Description for details. (Note: MemAddr12
is an output-only pin, does not have an
internal pullup or pulldown, and is not part
of the startup configuration.)
MemClk
5V
InOut
SDRAM Clock. Normally, this pin is an InOut,
outputting an internal PLL-generated 66.0
MHz or 72.0 MHz clock to the SDRAM and
receiving that same clock through its input
buffer. To bypass the PLL, set
/BypPLLMemClk = 0, and supply a 66.0 MHz
or 72.0 MHz clock to MemClk.
/BypPLLMemClk
5V/PU
In
Bypass PLL for MemClk. Normally, this pin is
a no-connect, and the internal pullup ensures
that the PLL is enabled. To bypass the PLL,
set /BypPLLMemClk = 0, and suppy a 66.0
MHz or 72.0 MHz clock to the MemClk pin
Host Interface
/HostWr_SCL
5V/H
In
186-Compatible Write when HostMode = 0.
Serial Clock when HostMode = 1.
/HostRd_SDA
5V/H
InOut
186-Compatible Read when HostMode = 0.
Serial Data (InOut, open drain output) when
HostMode = 1.
/HostCS
5V/PU
In
186-Compatible Chip Select when
HostMode=0. When HostMode=1, must be
tied to VDD or pulled up to VDD.
HostAddr[7:0]
5V/PD
In
186-Compatible Address when HostMode = 0.
No connect when HostMode = 1.
