41
Signal Group
Signal Name
Notes Type
Description
Video Output
/BypPLLClk48M
PU
In
Bypass PLL for Clk48M. Normally, this pin is
(continued)
a no-connect, and the internal pullup ensures
that the PLL is enabled. To bypass the PLL,
set /BypPLLClk48M = 0, and supply a 48.0
MHz clock to the Clk48M pin.
Clk54_72M
5V
InOut
54 or 72 MHz Clock. Normally, this pin is a
no-connect, outputting an internal PLL-
generated 54.0 MHz or 72.0 MHz clock and
receiving that same clock through its input
buffer. To bypass the PLL, set
/BypPLLClk54_72M = 0, and supply a 54.0
or 72.0 MHz clock to the Clk54_72M pin. -
/BypPLLClk54_72M
5V/PU
In
Bypass PLL for Clk54_72M. Normally, this
pin is a no-connect, and the internal pullup
ensures that the PLL is enabled. To bypass
the PLL, set /BypPLLClk54_72M = 0, and
supply a 54.0 MHz or 72.0 MHz clock to the
Clk54_72M pin.
Audio/Video
SDIn
5V/PD
In
Serial Digital Audio Input Data. See Audio/
Synchronization
Video Synchronization section of Functional
Description for audio formats supported.
WSIn
5V/PD
In
Serial Digital Audio Input Word Select. See
Audio/Video Synchronization section for audio
formats supported.
SCKIn
5V/PD
In
Serial Digital Audio Input Clock. Frequency
range of clock is 1.411 to 6.144 MHz. See
Audio/Video Synchronization section for
audio formats supported.
SDOut
Out
Serial Digital Audio Output Data. Audio
output follows audio input, with a delay equal
to that of the video processing pipeline.
WSOut
Out
Serial Digital Audio Output Word Select.
Audio output follows audio input, with a delay
equal to that of the video processing pipeline.
SCKOut
5V/PD
In
Serial Digital Audio Output Clock. Same
frequency as SCKIn. SDOut and WSOut are
generated from SCKOut. See Audio/Video
Synchronization section for more details on
on audio clocking.
Signal Group
Signal Name
Notes Type
Description
Host Interface
HostData[15:8]
5V/PD
InOut
186-Compatible Data when HostMode = 0.
(continued)
(VidInData[19:2])
Chroma video input data (16-bit & H/V syncs
format) when HostMode = 1.
HostData[7]
5V/PD
InOut
186-Compatible Data when HostMode = 0.
(VS)
Vertical sync input (8/16-bit & H/V syncs
format) when HostMode = 1.
HostData[6]
5V/PD
InOut
186-Compatible Data when HostMode = 0.
(HS)
Horizontal sync input (8/16-bit & H/V syncs
format) when HostMode = 1.
HostData[5:0]
5V/PD
InOut
186-Compatible Data when HostMode = 0.
No connnect when HostMode = 1.
HostClk
5V
InOut
186-Compatible Clock (33.33 MHz max) when
HostMode = 0. No Connect (27.0 MHz,
InOut) when HostMode = 1. Note that when
HostMode= 1, the clock output on HostClk
is also received and used internally.
HostMode
5V/PU
In
Serial Host Interface when HostMode = 1
(internal pullup defaults to this mode). 186-
compatible host interface when HostMode = 0.
Video Processing
/Det32PD
Out
3:2 Pulldown Sequence Detected.
Status
/Det22PD
Out
2:2 Pulldown Sequence Detected.
/DetVideo
Out
Interlaced Video Sequence Detected.
/DeintDone
Out
Deinterlace processing complete for current
field period. Opendrain output.
External APLL
/ExtRefSel
5V/PU
In
External APLL Reference Select. Internal
Reference Clock
pullup defaults pin to a 1, selecting VidInClk
as the APLL reference clock. To select
ExtRefXtalIn as the APLL reference clock,
set /ExtRefSel to a 0.
ExtRefXtalIn
In
External APLL Reference Crystal/oscillator
Input.
ExtRefXtalOut
Out
External APLL Reference Crystal Output.
QH21: SiI 504
Pin Descrtiption Notes:
1) A "/" preceding a signal name indicates that the signal is active low - i.e., that the signal is asserted or
active when low. All other signals are active high.
2) Abbreviations in Notes column of pinout table:
5V:
5 volt tolerant input
PU:
internal pullup
PD:
internal pulldown
H:
Hysteresis on input
3) The pins HostData[15:6] are used for two distinct functions. When HostMode = 0, these pins are 186-
compatible data pins. When HostMode = 1, they may be either no connects, or are used for the non-656
video input port. This dual functionality is noted in the pin description table with the unused signal function
name in parentheses, and in the Pin Number table and Pin Diagram with the dual pin function names sepa-
rated by a backslash ("\").
4) Pins marked "Reserved" should be left unconnected - i.e., they should not be pulled up, pulled down,
grounded, connected to a power supply source, or any other signal.
Signal Group
Signal Name
Notes Type
Description
Reset
/Reset
5V/H
In
Hardware Reset.
Test
Test[1:0]
5V/PD
In
Production hardware test support.
PuPdDis
5V
In
Internal pullup and pulldown disable test
function. Connect to ground for normal
operation.
Power
AVDD
Pwr
1.8V Analog Power for PLL. (Qty: 1)
ARTN
Pwr
Analog Return for PLLs. (Qty: 1)
VDDCore
Pwr
1.8V Core Power. (Qty: 11)
GNDCore
Pwr
Digital Ground for Core Power. (Qty: 12)
VDDIO
Pwr
3.3V I/O Power. (Qty: 11)
GNDIO
Pwr
Digital Ground for I/O Power. (Qty: 18)
