MAI Basic Four 2000 Series, Руководство по обслуживанию

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BFISD 8079
3.2.16.5 MMU Address Translation
The MMU translates address bits A09+ through A23+ from the 68010. Bits A01+
through A08+ are not translated but go directly to the memory (thus setting the
inimum segment size to 512 bytes). (Address bit A00 does not exist outside the
68010. This bit is used internal to the 68010, in conjunction with the data
size specification of each instruction, to generate the two UDS- and LDS-
signals [Upper Data Strobe and Lower Data Strobe]. These determine which byte
of a 16-bit [word-wide] memory location is being addressed.)
The resulting address translation provides each user with eight variable-length
memory segments (which are transparent to the user), in physical memory (RAM).
Each segment has associated with it a 12-bit base address, a 12-bit limit ad-
dress, 4 bits of segment attributes and 4 bits of segment status. These 32
bits of information (called a segment descriptor) are stored at one address in
eight 74S189 16- X 4-bit storage registers (3W, 3X, 3Y, 3Z, 4X, 4Y, 4Z and 7X).
(Refer to the CMB Logic Diagram, sheets 30 through 34.)
The eight registers are in parallel with respect to the address lines connected
to them. Only eight of the sixteen available 4-bit registers in each of the
eight storage registers are used. Hence, all of the A3 address inputs to the
74S189s are pulled low.
Each of the eight segment registers is addressed by signals MFA1+, MFA2+, and
MFA3+. These come from a 74S157 l-of-2 data selector (3T). (Refer to the CMB
Logic Diagram, sheet 32.) Address bits A01+A, A02+A, and A03+A are selected
when the 68010 is in the supervisor mode; A21+, A22+, and A23+ are selected in
the user mode. Thus, when in the supervisor mode, the 68010 addresses the seg-
ment registers to update the segment descriptors; and, when in the user mode,
the 68010 addresses these registers to perform address translation. The CFC2-
(CPU Function Code 2, explained in paragraph 3.2.2) signal into the data selec-
tor (3T) performs the selection. In the multi-user mode, the operating system
software loads the next user's segment descriptors into the segment registers
with each context switch.
Base Address
The base addresses are stored in three 74S189 storage registers (3X, 3Y, and
3Z). (Refer to the CMB Logic Diagram, sheets 30 and 31.) The operating system
software does this (in the supervisor mode) by writing to the input/output ad-
dress (8XXXXX [hex]) that enables signal MMBWE- (paragraph 3.2.12.2). The seg-
ment base descriptor word format is as follows:
15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
R X TYPE A20 A19 A18 A17 A16 A15 A14 A13 A12 All A10 A09
(Attributes R, X and TYPE are explained in paragraph 3.2.16.6.) During a 68010
memory cycle, the physical addresses represented by bits A09 through A20 are
obtained by summing the base address, contained in the three storage registers,
with the logical addresses represented by bits A09 through A20, from the 68010.
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