MAI Basic Four 2000 Series, Руководство по обслуживанию

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BFISD 8079
Then, as in the autovectored case, the content of the vector number (after
multiplication by four) is fetched and then loaded into the 68010 program
counter, and normal instruction execution begins in the interrupt service
routine. This is the bus-vectored interrupt mode of the 68010.
The data selector (10K) thus is used to switch between autovectoring and bus-
vectoring for interrupt levels 2 and 4. The data selector is enabled only when
signal FDC7- (Function DeCode 7) is asserted, signifying an interrupt acknowl-
edge cycle is in process.
3.2.6.2 Interrupt Acknowledge Decoder
At the same time that the priority number on the address bus was being decoded
to produce CVPA-, a 74LS138 l-of-8 decoder (10L, CMB Logic Diagram, sheet 20)
also decoded those address bits. The IACKL3-, IACKL5- and IACKL7- (Interrupt
ACKnowledge Levels 3, 5 and 7) signals are direct outputs. IACKL3- is used by
the floppy disk controller, IACKL5- enables the byte multiplexer control logic,
and IACKL7- is used by the interrupt control logic and the parity logic. Two
signals, IACKL5- and IACKL7-, also are decoded with the other decoder outputs
to create signals RIACK+ and RIACK- (I/O bus Requester Interrupt ACKnowledge).
RIACK+ provides the Processor Data Transfer ACKnowledge (PDTACK-) signal back
to the 68010, and RIACK- provides the data bus direction control. Like the
data selector, the decoder (10L) is enabled when FDC7- (Function DeCode 7) is
active, and indicates a 68010 interrupt acknowledge cycle is in process.
3.2.7 Reset and Power Fail Detection Logic
The Central Microprocessor Board contains logic circuitry for three forms of
reset: (1) power-on, (2) button, and (3) software.
Power-on reset and button reset are electrically similar. Power-on reset is
automatic on power-up and generates a 100- to 800-millisecond reset pulse via
an NE555 timer (5B). (Refer to the CMB Logic Diagram, sheet 21.) Power-on
reset also generates a level 7 interrupt.
Button reset is actuated by the case-mounted switch, which is debounced by a
74LS00 NAND gate (4E). The output is RSTF2+, the master ReSeT Flag signal.
The signal becomes POR- (Power-On Reset), which maps the boot PROM in all mem-
ory; generates HLT- (HaLT) for the 68010; and generates a RESET- for the system
I/O bus and a CRESET- for devices on the Central Microprocessor Board.
The 68010 has a bidirectional reset pin (RST-), which receives the reset signal
during a power-on reset or a button reset. On a software-created reset, the
68010 pulls RST- low, which causes the reset circuitry to issue a RESET- to the
system I/O bus and a CRESET- for devices on the Central Microprocessor Board.
The signal PFD+ (Power Fail Detect) comes in on the system I/O bus to warn that
power supply failure is imminent and generates an INT7- (INTerrupt level 7, the
non-maskable interrupt).
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