MAI Basic Four 2000 Series, Руководство по обслуживанию

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BFISD 8079
a. The priority bus signals indicate the highest number of four groups
of four devices, one or more of which is requesting the system I/O
bus. The group with the highest priority number on the bus qualifies
to continue with the second step; any competing groups with smaller
numbers may continue the bus request signal (BR-1).
b. During the second half of the clock period, the priority bus signals
indicate the highest number of the four devices within the qualified
group. At the end of the clock period, the contending device with the
highest priority number responds to the bus grant signal (PBG-).
After a system I/O bus device controller or the refresh circuitry has received
the bus grant signal (PBG-), the responding device must monitor the following
three signals to determine when the system I/O bus actually is available for
use.
• Address strobe (AS-) - must be negated, indicating that the 68010, or
another bus master, has completed the current bus cycle
• Data transfer acknowledge signal (DTACK-) - must be negated, indicating
that the slave device accessed by the 68010 is no longer on the main
memory data bus
• Bus grant acknowledge signal (CBACK-) -must be negated, indicating that
no other peripheral device controller presently is using the system I/O
bus
The winning device must wait until allthese conditions are met before it may
assume control of the system I/O bus. When the conditions are met, the device
taking the bus leaves its priority number on the priority bus and asserts the
BGACK- signal. BGACK- is buffered by a 74S244 tristate driver (1E) and sent to
the 68010 as CBACK-. There is at least a one-clock-period delay between CBACK-
and PBG-; it is during this period the prospective bus masters arbitrate. (A
74S240 inverter [1Y] increases the drive capability of CBACK+; signals CBACK-
and CBACK+ are delivered throughout the Central Microprocessor Board to enable
various other signals.)
3.2.11.2 Fast Bus Grant
When the asserted bus grant (PBG-) signal was sent to the controllers, it was
ORed with signal FBG- (Fast Bus Grant) in a 74LS08 AND gate (7T). The output
from the gate is buffered by a 74S244 tristate driver (1E) and then placed on
the system I/O bus (connector J01, pin C13) , to be delivered to the peripheral
device controller boards. The fast bus grant signal is generated to give the
controllers more time for bus arbitration during heavy DMA activity.
Signal FBG- is asserted only when a 68010 memory bus cycle is underway and the
68010 would give a bus grant anyway. FBG— is asserted on the falling edge of
the K8MHZ- clock when (a) there is a bus request, (b) the address strobe is ac-
tive, and (c) timing signal CSTOF+ still is low. Although the resulting window
is not very long, it can help to speed up heavy DMA activity.
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