page 48
Monitoring bus voltage
Right from switching on the machine, the bus voltage is monitored directly by the DSP of the DRV.
The actual value of the bus voltage is send from the DSP of the DRV to the MAPRO.
As soon as the voltage gets too high, the machine stops with
E02
“Overvoltage”. In this case the power-up relays
on the DRV are switched off, so that the power-up resistors are active again, lowering the input voltage.
If the minimum value of 390V DC is not reached during startup (switching on), the machine stops with
E22-03
“Undervoltage Startup”.
Schematic
RE1
RE2
X17
1
2
3
4
-Uz
+Uz1
+Uz2
-Uz2
TM2
TM1
DSP
X2-3*
X2-4*
FPGA
X7-4
X7-5
MAPRO
DRV
RS485
RS485
*(at the DRV05 the connector designation X19 was later renamed into X2)
In general the values of both bus voltages at the power modules TM1 and TM2 are equal (symmetrical). If there
should be a difference >60V, the machine stops with
E33-01
Unsymmetrical bus voltage.
If a difference >60V is detected during startup, the machine stops with
E33-02
Unsymmetrical bus voltage Startup.
As soon as the difference gets below 60V, the error code is reset.
Code Cause
E02-02
During startup the maximum limit of 700V DC was exceeded.
E02-04
The maximum limit of 750V DC (or 400V DC at the modules) was exceeded during operation.
E02-05
The FPGA measured a too high bus voltage (>400V DC) at the modules.
E22-03 During startup the minimum limit of 390V DC was not reached.
E33-01
The difference between the bus voltages of module 1 and 2 is greater 60V.
E33-02
The difference between the bus voltages of module 1 and 2 is greater 60V at startup.
