Linear LTC2345 Скачать руководство пользователя страница 5 | Manualshive

Страница: 5 / 10

Linear LTC2345 Скачать руководство пользователя страница 5

5

dc2326af

DEMO MANUAL DC2326A

Dc2326a setup

Layout

As with any high performance ADC, this part is sensitive

to layout. The area immediately surrounding the ADC on

the DC2326A should be used as a guideline for placement,

and routing of the various components associated with

the ADC. Here are some things to remember when laying

out a board for the LTC2345. A ground plane is necessary

to obtain maximum performance. Keep bypass capacitors

as close to supply pins as possible. Use individual low

impedance returns for all bypass capacitors. Use of a

symmetrical layout around the analog inputs will minimize

the effects of parasitic elements. Shield analog input traces

with ground to minimize coupling from other traces. Keep

traces as short as possible.

Component Selection

When driving a low noise, low distortion ADC such as the

LTC2345, component selection is important so as to not

degrade performance. Resistors should have low values

to minimize noise and distortion. Metal film resistors are

recommended to reduce distortion caused by self heat-

ing. Because of their low voltage coefficients, to further

reduce distortion NPO or silver mica capacitors should be

used. Any buffer used to drive the LTC2345 should have

low distortion, low noise and a fast settling time such as

the LT1355.

«
...
3
4
5
6
7
...
»

Содержание LTC2345

Страница 1: ...l and SoftSpan are trademarks of Linear Technology Corporation All other trademarks are the property of their respective owners assembly options Board Photo demonstrate DC performance such as peak to peak noise and DC linearity Use the DC890 if precise sampling rates are required or to demonstrate AC performance such as SNR THD SINAD and SFDR The DC2326A is intended to demonstrate recommended grou...

Страница 2: ...lp menu Updates can be downloaded from the Tools menu Check for updates periodically as new features may be added The PScope software should recognize the DC2326A and configure itself automatically Click the Collect button See Figure 3 to begin acquiring data The Collect button then changes to Pause which can be clicked to stop data acquisition dc590 dc2026 Quick Start Procedure IMPORTANT To avoid...

Страница 3: ...it is recommended for lower sample rates to divide down a higher frequency clock to the desired sample rate The ratio of clock frequency to conversion rate is shown in the Assembly Options table If theclockinputistobedrivenwithlogic itisrecommended that the 49 9Ω termination resistor R4 be removed Driving R4 with discrete logic may result in slow rising edges TheseslowrisingedgesmaycompromisetheSN...

Страница 4: ...Options button in the PScope tool bar shown in Figure 4 This will open the Configure Channels menu of Figure 5 In this menu it is possible to set the input signal range setting for each channel There is also a button to return PScope to the default DC2326A settings which are optimized for the default hardware settings of the DC2326A Thereareanumberofscenariosthatcanproducemislead ing results when ...

Страница 5: ...of a symmetricallayoutaroundtheanaloginputswillminimize theeffectsofparasiticelements Shieldanaloginputtraces with ground to minimize coupling from other traces Keep traces as short as possible Component Selection When driving a low noise low distortion ADC such as the LTC2345 component selection is important so as to not degrade performance Resistors should have low values to minimize noise and d...

Страница 6: ...6 dc2326af DEMO MANUAL DC2326A DC2326A Setup Figure 3 PScope Screen Shot Figure 4 PScope Tool Bar ...

Страница 7: ...7 dc2326af DEMO MANUAL DC2326A DC2326A Setup Figure 5 PScope Configuration Menu ...

Страница 8: ...8 dc2326af DEMO MANUAL DC2326A DC2326A Setup Figure 6 QuikEval Screen Shot Figure 7 QuikEval Configuration Menu ...

Страница 9: ... logic levels The default setting is CMOS Only CMOS is currently supported Definitions P1 DC890 interface is used to communicate with the DC890 controller J1 CLK provides the master clock for the DC2326A when interfaced to the DC890 J2 FPGA PROGRAM is used to program the FPGA This is for factory use only JP4 EEPROM is for factory use only The default posi tion is WP JP5 JP12 AIN0 AIN7 can be used ...

Страница 10: ...UDING ANY WARRANTY OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE EXCEPT TO THE EXTENT OF THIS INDEMNITY NEITHER PARTY SHALL BE LIABLE TO THE OTHER FOR ANY INDIRECT SPECIAL INCIDENTAL OR CONSEQUENTIAL DAMAGES The user assumes all responsibility and liability for proper and safe handling of the goods Further the user releases LTC from all claims arising from the handling or use of the goo...

Отзывы:

Нет отзывов