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dc2326af

DEMO MANUAL DC2326A

Reference

The  default  reference  is  the  LTC2345  internal 4.096V 

reference. Alternatively, if a higher reference voltage is 

desired, the LTC6655-5 reference (U7) can be used by 

setting  the  REF  jumper (JP1)  to  the  EXT  position  and 

installing a 0Ω resistor in the R7 position. This should 

result in better SNR performance but may slightly degrade 

the THD performance of the LTC2345. 

Analog Inputs

All eight inputs have the same driver circuitry. The circuit of 

Figure 2 shows the driver for IN0. It provides a DC coupled 

single-ended to fully differential output to the analog inputs 

of the LTC2345 with a maximum 0V-4.096V input signal. 

DC890 Data Collection

For SINAD, THD or SNR testing a low noise, low distortion 

generator such as the B&K Type 1051 or Stanford Research 

SR1 should be used. A low jitter RF oscillator such as the 

Rohde & Schwarz SMB100A is used to drive the clock 

input. This demo board is tested in house by attempting 

to duplicate the FFT plot shown in Typical Performance 

Characteristics section of the LTC2345 data sheet. This 

involves using a 60MHz clock source, along with a sinu-

soidal generator at a frequency of approximately 2kHz. The 

input signal level is approximately –1dBFS. A typical FFT 

obtained with DC2326A is shown in Figure 3. Note that 

to calculate the real SNR, the signal level (F1 amplitude = 

–1.099dB) has to be added back to the SNR that PScope 

displays. With the example shown in Figure 3 this means 

that  the  actual  SNR  would  be 91.40dB  instead  of  the 

90.30dB that PScope displays. Taking the RMS sum of the 

recalculated SNR and the THD yields a SINAD of 91.39dB 

which is fairly close to the typical number for this ADC.

Dc2326a setup

To change the default settings for the LTC2345 in PScope, 

click on the Set Demo Bd Options button in the PScope 

tool bar shown in Figure 4. This will open the Configure 

Channels menu of Figure 5. In this menu it is possible to 

set the input signal range setting for each channel. There 

is also a button to return PScope to the default DC2326A 

settings  which  are  optimized  for  the  default  hardware 

settings of the DC2326A.
There are a number of scenarios that can produce mislead-

ing results when evaluating an ADC. One that is common 

is feeding the converter with an input frequency that is 

a sub-multiple of the sample rate, and which will only 

exercise  a  small  subset  of  the  possible  output  codes. 

The proper method is to pick an M/N frequency for the 

input sine wave frequency. N is the number of samples 

in the FFT. M is a prime number between one and N/2. 

Multiply M/N by the sample rate to obtain the input sine 

wave  frequency.  Another  scenario  that  can  yield  poor 

results is if you do not have a signal generator capable of 

ppm frequency accuracy or if it cannot be locked to the 

clock frequency. You can use an FFT with windowing to 

reduce the “leakage” or spreading of the fundamental, to 

get a close approximation of the ADC performance. If an 

amplifier or clock source with poor phase noise is used, 

the windowing will not improve the SNR.

DC590/DC2026 Data Collection

Due  to  the  relatively  low  and  somewhat  unpredictable 

sample rate of the DC590/DC2026 its usefulness is lim-

ited to noise measurement and data collection of slowly 

moving signals. A typical data capture and histogram are 

shown in Figure 6. To change the default settings for the 

LTC2345 in QuikEval, click on the Sequence Config but-

ton. This will open the Config Dialog menu of Figure 7.  

In this menu it is possible to set the input signal range 

and gain compression setting for each sequence. There 

is also a button to return QuikEval to the default DC2326A 

settings which are optimized for the default hardware set-

tings of the DC2326A.

Содержание LTC2345

Страница 1: ...l and SoftSpan are trademarks of Linear Technology Corporation All other trademarks are the property of their respective owners assembly options Board Photo demonstrate DC performance such as peak to peak noise and DC linearity Use the DC890 if precise sampling rates are required or to demonstrate AC performance such as SNR THD SINAD and SFDR The DC2326A is intended to demonstrate recommended grou...

Страница 2: ...lp menu Updates can be downloaded from the Tools menu Check for updates periodically as new features may be added The PScope software should recognize the DC2326A and configure itself automatically Click the Collect button See Figure 3 to begin acquiring data The Collect button then changes to Pause which can be clicked to stop data acquisition dc590 dc2026 Quick Start Procedure IMPORTANT To avoid...

Страница 3: ...it is recommended for lower sample rates to divide down a higher frequency clock to the desired sample rate The ratio of clock frequency to conversion rate is shown in the Assembly Options table If theclockinputistobedrivenwithlogic itisrecommended that the 49 9Ω termination resistor R4 be removed Driving R4 with discrete logic may result in slow rising edges TheseslowrisingedgesmaycompromisetheSN...

Страница 4: ...Options button in the PScope tool bar shown in Figure 4 This will open the Configure Channels menu of Figure 5 In this menu it is possible to set the input signal range setting for each channel There is also a button to return PScope to the default DC2326A settings which are optimized for the default hardware settings of the DC2326A Thereareanumberofscenariosthatcanproducemislead ing results when ...

Страница 5: ...of a symmetricallayoutaroundtheanaloginputswillminimize theeffectsofparasiticelements Shieldanaloginputtraces with ground to minimize coupling from other traces Keep traces as short as possible Component Selection When driving a low noise low distortion ADC such as the LTC2345 component selection is important so as to not degrade performance Resistors should have low values to minimize noise and d...

Страница 6: ...6 dc2326af DEMO MANUAL DC2326A DC2326A Setup Figure 3 PScope Screen Shot Figure 4 PScope Tool Bar ...

Страница 7: ...7 dc2326af DEMO MANUAL DC2326A DC2326A Setup Figure 5 PScope Configuration Menu ...

Страница 8: ...8 dc2326af DEMO MANUAL DC2326A DC2326A Setup Figure 6 QuikEval Screen Shot Figure 7 QuikEval Configuration Menu ...

Страница 9: ... logic levels The default setting is CMOS Only CMOS is currently supported Definitions P1 DC890 interface is used to communicate with the DC890 controller J1 CLK provides the master clock for the DC2326A when interfaced to the DC890 J2 FPGA PROGRAM is used to program the FPGA This is for factory use only JP4 EEPROM is for factory use only The default posi tion is WP JP5 JP12 AIN0 AIN7 can be used ...

Страница 10: ...UDING ANY WARRANTY OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE EXCEPT TO THE EXTENT OF THIS INDEMNITY NEITHER PARTY SHALL BE LIABLE TO THE OTHER FOR ANY INDIRECT SPECIAL INCIDENTAL OR CONSEQUENTIAL DAMAGES The user assumes all responsibility and liability for proper and safe handling of the goods Further the user releases LTC from all claims arising from the handling or use of the goo...

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