16
Rev. B
For more information
PIN FUNCTIONS
and MFR_ADC_CONTROL COMMAND section. When
operating from 4.5V to 5.75V with no auxiliary bias sup-
ply, then the main input supply should connect to SV
IN
and INTV
CC
. See Test Circuit 2 for an example. In this
configuration, the ICHIP current will not be relevant since
INTV
CC
is connected to SV
IN
.
I
IN
+
(J1):
Positive Current Sense Amplifier Input. If the
input current sense amplifier is not used, this pin must
be shorted to the I
IN
–
and SV
IN
pin. See Operation section
for detail about the input current sensing.
I
IN
–
(K1):
Negative Current Sense Amplifier Input. If the
input current sense amplifier is not used, this pin must
be shorted to the I
IN
+
and SV
IN
pin. See Operation section
for detail about the input current sensing.
EXTV
CC
(F8):
External Power Input to an Internal Switch
Connected to INTV
CC
. This switch closes and supplies
the IC power, bypassing the internal regulator whenever
EXTV
CC
is higher than 4.7V and V
IN
is higher than 7V.
EXTV
CC
also powers up V
DD33
when EXTV
CC
is higher than
4.7V and INTV
CC
is lower than 3.8V. Do not exceed 6V
on this pin. Decouple this pin to PGND with a minimum
of 4.7µF low ESR tantalum or ceramic capacitor. If the
EXTV
CC
pin is not used to power INTV
CC
, the EXTV
CC
pin
must be tied GND.
INTV
CC
(E7) :
Internal Regulator, 5.5V Output. When
operating the LTM4680 from 5.75V ≤ SV
IN
≤ 16V, an
LDO generates INTV
CC
from SV
IN
to bias internal control
circuits and the MOSFET drivers of the LTM4680. An
external 2.2µF ceramic decoupling is required. INTV
CC
is
regulated regardless of the RUN
n
pin state. When operat-
ing the LTM4680 with 4.5V ≤ SV
IN
< 5.75V, INTV
CC
must
be electrically shorted to SV
IN
.
V
DD33
(E8):
Internally Generated 3.3V Power Supply
Output Pin. This pin should only be used to provide exter-
nal current for the pull-up resistors required for
FAULT
n
,
SHARE_CLK, and SYNC, and may be used to provide
external current for pull-up resistors on RUN
n
, SDA, SCL,
ALERT
and PGOOD
n
. No external decoupling is required.
V
DD25
(D12):
Internally Generated 2.5V Power Supply
Output Pin. Do not load this pin with external current;
it is used strictly to bias internal logic and provides cur-
rent for the internal pull-up resistors connected to the
configuration-programming pins. No external decoupling
is required.
ASEL (F12):
Serial Bus Address Configuration Pin. On
any given I
2
C/SMBus serial bus segment, every device
must have its own unique slave address. If this pin is left
open, the LTM4680 powers up to its default slave address
of 0x4F (hexadecimal), i.e., 1001111b (industry-standard
convention is used throughout this document: 7-bit slave
addressing). The lower four bits of the LTM4680’s slave
address can be altered from this default value by connect-
ing a resistor from this pin to SGND. Minimize capaci-
tance—especially when the pin is left open—to assure
accurate detection of the pin state. See Table 4.
FSWPH_CFG (E9):
Switching Frequency, Channel
Phase-Interleaving Angle and Phase Relationship to
SYNC Configuration Pin. If this pin is left open—or, if the
LTM4680 is configured to ignore pin-strap (RCONFIG)
resistors, i.e., MFR_CONFIG_ALL[6] = 1b—then
LTM4680’s switching frequency (FREQUENCY_SWITCH)
and channel phase relationships (with respect to the SYNC
clock; MFR_PWM_CONFIG[2:0]) are dictated at SV
IN
power-up according to the LTM4680’s NVM contents.
Default factory values are: 575kHz operation; channel 0
at 0°; and channel 1 at 180°C (convention throughout
this document: a phase angle of 0° means the chan-
nel’s switch node rises coincident with the falling edge
of the SYNC pulse). Connecting a resistor from this pin
to SGND (and using the factory-default NVM setting of
MFR_CONFIG_ALL[6] = 0b) allows a convenient way to
configure multiple LTM4680s with identical NVM contents
for different switching frequencies of operation and phase
interleaving angle settings of intra- and extra-module-
paralleled channels—all, without GUI intervention or the
need to “custom pre-program” module NVM contents.
(See the Operation section.) Minimize capacitance—espe-
cially when the pin is left open—to assure accurate detec-