22
LTC1736
to 15A in 100ns or 15A to 0.2A in 100ns. The voltage at the
microprocessor must be held to about
±
0.1V of nominal
in spite of these load current steps. Since the control loop
cannot respond this fast, the output capacitors must
supply the load current until the control loop can respond.
Capacitor ESR and ESL primarily determine the amount of
droop or overshoot in the output voltage. Normally, sev-
eral capacitors in parallel are required to meet micropro-
cessor transient requirements.
Active voltage positioning is a form of deregulation. It
sets the output voltage high for light loads and low for
heavy loads. When load current suddenly increases, the
output voltage starts from a level higher than nominal so
the output voltage can droop more and stay within the
specified voltage range. When load current suddenly
decreases the output voltage starts at a level lower than
nominal so the output voltage can have more overshoot
and stay within the specified voltage range. Less output
capacitance is required when voltage positioning is used
because more voltage variation is allowed on the output
capacitors.
Active voltage positioning can be implemented using the
OPTI-LOOP architecture of the LTC1736 with two external
resistors. An input voltage offset is introduced when the
error amplifier has to drive a resistive load. This offset is
limited to
±
30mV at the input of the error amplifier. The
resulting change in output voltage is the product of input
offset and the feedback voltage divider ratio.
Figure 6 shows a CPU-core-voltage regulator with active
voltage positioning. Resistors R1 and R5 force the input
voltage offset that sets the output voltage according to the
load current level. To select values for R1 and R5, first
determine the amount of output deregulation allowed. The
actual specification for a typical microprocessor allows
the output to vary
±
0.112V. The LTC1736 output voltage
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
C
OSC
RUN/SS
I
TH
FCB
SGND
PGOOD
SENSE
–
SENSE
+
V
FB
V
OSENSE
VID0
VID1
TG
BOOST
SW
V
IN
INTV
CC
BG
PGND
EXTV
CC
VIDV
CC
VID4
VID3
VID2
LTC1736
C5
1000pF
C6
47pF
VID0
VID1
VID2
VID3
VID4
VID
INPUT
C7 330pF
C3
100pF
C1 39pF
C4 100pF
C2
0.1
µ
F
POWER
GOOD
R2
100k
R5
100k
R4
100k
R3
680k
R1
27k
+
C10
1
µ
F
5V (OPTIONAL)
C18
1
µ
F
C12 TO C14
10
µ
F
35V
C11
4.7
µ
F
10V
D1
CMDSH-3
C8
0.1
µ
F
D2
MBRS340
C9
0.22
µ
F
M1
FDS6680A
L1
1
µ
H
R6
0.003
Ω
M2, M3
FDS6680A
×
2
1736 F06
C15 TO C17
180
µ
F/4V
×
4
V
OUT
0.9V TO 2V
15A
GND
GND
V
IN
7.5V TO 24V
+
C10, C18: TAIYO YUDEN JMK107BJ105
C11: KEMET T494A475M010AS
C12 TO C14: TAIYO YUDEN GMK325F106
C15 TO C17: PANASONIC EEFUE0G181R
D1: CENTRAL SEMI CMDSH-3
D2: MOTOROLA MBRS340
L1: PANASONIC ETQP6F1R0SA
M1 TO M3: FAIRCHILD FDS6680A
R6: IRC LRF2512-01-R003-J
U1: LINEAR TECHNOLOGY LTC1736CG
Figure 6. CPU-Core-Voltage Regulator with Active Voltage Positioning
APPLICATIO S I FOR ATIO
W
U
U
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