12
LTC1736
APPLICATIO S I FOR ATIO
W
U
U
U
molypermalloy or Kool M
µ
®
cores. Actual core loss is
independent of core size for a fixed inductor value, but it
is very dependent on the inductance selected. As induc-
tance increases, core losses go down. Unfortunately,
increased inductance requires more turns of wire and
therefore copper losses will increase.
Ferrite designs have very low core loss and are preferred
at high switching frequencies, so design goals can con-
centrate on copper loss and preventing saturation. Ferrite
core material saturates “hard,” which means that induc-
tance collapses abruptly when the peak design current is
exceeded. This results in an abrupt increase in inductor
ripple current and consequent output voltage ripple. Do
not allow the core to saturate!
Molypermalloy (from Magnetics, Inc.) is a very good, low
loss core material for toroids, but it is more expensive than
ferrite. A reasonable compromise from the same manu-
facturer is Kool M
µ
. Toroids are very space efficient,
especially when you can use several layers of wire. Be-
cause they generally lack a bobbin, mounting is more
difficult. However, designs for surface mount are available
that do not increase the height significantly.
Power MOSFET and D1 Selection
Two external power MOSFETs must be selected for use
with the LTC1736: An N-channel MOSFET for the top
(main) switch and an N-channel MOSFET for the bottom
(synchronous) switch.
The peak-to-peak gate drive levels are set by the INTV
CC
voltage. This voltage is typically 5.2V during start-up. (See
EXTV
CC
Pin Connection.) Consequently, logic-level thresh-
old MOSFETs must be used in most LTC1736 applica-
tions. The only exception is when low input voltage is
expected (V
IN
< 5V); then, sublogic level threshold
MOSFETs (V
GS(TH)
< 3V) should be used. Pay close
attention to the BV
DSS
specification for the MOSFETs as
well; most of the logic level MOSFETs are limited to 30V or
less.
Selection criteria for the power MOSFETs include the “ON”
resistance R
DS(ON)
, reverse transfer capacitance C
RSS
,
input voltage and maximum output current. When the
LTC1736 is operating in continuous mode the duty cycles
for the top and bottom MOSFETs are given by:
Main Switch Duty Cycle
V
V
Synchronous Switch Duty Cycle
V
V
V
OUT
IN
IN
OUT
IN
=
=
–
The MOSFET power dissipations at maximum output
current are given by:
P
V
V
I
R
k V
I
C
f
P
V
V
V
I
R
MAIN
OUT
IN
MAX
DS ON
IN
MAX
RSS
SYNC
IN
OUT
IN
MAX
DS ON
=
( )
+
( )
+
( ) ( )( )( )
=
( )
+
( )
2
2
2
1
1
δ
δ
(
)
(
)
–
where
δ
is the temperature dependency of R
DS(ON)
and k
is a constant inversely related to the gate drive current.
Both MOSFETs have I
2
R losses while the topside
N-Channel equation includes an additional term for tran-
sition losses, which are highest at high input voltages. For
V
IN
< 20V the high current efficiency generally improves
with larger MOSFETs, while for V
IN
> 20V the transition
losses rapidly increase to the point that the use of a higher
R
DS(ON)
device with lower C
RSS
actually provides higher
efficiency. The synchronous MOSFET losses are greatest
at high input voltage or during a short circuit when the duty
cycle in this switch is nearly 100%.
The term (1 +
δ
) is generally given for a MOSFET in the
form of a normalized R
DS(ON)
vs Temperature curve, but
δ
= 0.005/
°
C can be used as an approximation for low
voltage MOSFETs. C
RSS
is usually specified in the MOSFET
characteristics. The constant k = 1.7 can be used to
estimate the contributions of the two terms in the main
switch dissipation equation.
The Schottky diode D1 shown in Figure 1 conducts during
the dead-time between the conduction of the two power
MOSFETs. This prevents the body diode of the bottom
MOSFET from turning on and storing charge during the
dead-time, which could cost as much as 1% in efficiency.
A 3A Schottky is generally a good size for 10A to 12A
regulators due to the relatively small average current.
Kool M
µ
is a registered trademark of Magnetics, Inc.
