LMS7002M Quick Starter Manual for EVB7 kit
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P a g e
Version: 2.2
Last modified: 29/09/2014
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RxTSPCLK is selected.
MCLK2 clock source
Select MCKL2 clock source from: RxTSPCLKA, TxTSPCLKA, RxTSPCLKA after
divider or TxTSPCLKA after divider. By default RxTSPCLK after divider is selected.
MCLK1 clock source
Select MCKL1 clock source from: RxTSPCLKA, TxTSPCLKA, RxTSPCLKA after
divider or TxTSPCLKA after divider. By default TxTSPCLK after divider is selected.
TxTSPCLKA
clock
divider
TxTSP clock divider, used to produce MCLK(1/2) clocks. Control range from 0 to
255. By default set to 255.
RxTSPCLKA
clock
divider
RxTSP clock divider, used to produce MCLK(1/2) clocks. Control range from 0 to
255. By default set to 255.
Enable Tx clock divider
Enables Tx clock divider. Set to enable by default.
FCLK1 invert
Inverts FCLK1 clock. By default clock is not inverted.
Enable Rx clock divider
Enables Rx clock divider. Set to enable by default.
FCLK2 invert
Inverts FCLK1 clock. By default clock is not inverted.
MCLK1DLY
Select MCLK1 clock delay. By default clock not delayed.
MCLK2DLY
Select MCLK2 clock delay. By default clock not delayed.
Direction controls
DIQ2 mode
DIQ2 direction control mode. By default set to Automatic.
DIQ1 mode
DIQ1 direction control mode. By default set to Automatic.
DIQ2 direction
DIQ2 direction. By default set to Input.
DIQ1 direction
DIQ1 direction. By default set to Input.
ENABLE2 mode
ENABLE2 direction control mode. By default set to Automatic.
ENABLE1 mode
ENABLE1 direction control mode. By default set to Automatic.
ENABLE2 direction
ENABLE2 direction. By default set to Input.
ENABLE1 direction
ENABLE1 direction. By default set to Input.
LML1
Clock cycles to wait
before data drive stop
Controls the number of clock cycles to wait before data drive stop after burst stop is
detected in JESD207 mode on Port 1 and Port 1 is transmitter. By default set to 1.
Clock cycles to wait
before data drive start
Controls the number of clock cycles to wait before data drive stop after burst start is
detected in JESD207 mode on Port 1 and Port 1 is transmitter. By default set to 1.
Clock cycles to wait
before data capture stop
Controls the number of clock cycles to wait before data capture stop after burst stop is
detected in JESD207 mode on Port 1 and Port 1 is receiver. By default set to 1.
Clock cycles to wait
before data capture stop
Controls the number of clock cycles to wait before data capture stop after burst start is
detected in JESD207 mode on Port 1 and Port 1 is receiver. By default set to 1.
LML2
Clock cycles to wait
before data drive stop
Controls the number of clock cycles to wait before data drive stop after burst stop is
detected in JESD207 mode on Port 1 and Port 1 is transmitter. By default set to 1.
Clock cycles to wait
before data drive start
Controls the number of clock cycles to wait before data drive stop after burst start is
detected in JESD207 mode on Port 1 and Port 1 is transmitter. By default set to 1.
Clock cycles to wait
before data capture stop
Controls the number of clock cycles to wait before data capture stop after burst stop is
detected in JESD207 mode on Port 1 and Port 1 is receiver. By default set to 1.
Clock cycles to wait
before data capture stop
Controls the number of clock cycles to wait before data capture stop after burst start is
detected in JESD207 mode on Port 1 and Port 1 is receiver. By default set to 1.
Direction controls
DIQ2 mode
DIQ2 direction control mode for port 2. Set to Automatic by default.
DIQ1 mode
DIQ1 direction control mode for port 1. Set to Automatic by default.
DIQ2 direction
DIQ2 direction. Set to input by default.
DIQ1 direction
DIQ1 direction. Set to input by default.
ENABLE2 mode
ENABLE2 direction control mode. Set to Automatic by default.
ENABLE1 mode
ENABLE1 direction control mode. Set to Automatic by default.
ENABLE2 direction
ENABLE2 direction. Set to input by default.
ENABLE1 direction
ENABLE1 direction. Set to input by default.
