6. BLOCK DIAGRAM
- 129 -
Copyright © 2012 LG Electronics. Inc. All right reserved.
Only for training and service purposes
LGE Internal Use Only
XMM6260
(Infineon)
Transceiver
PMB5712
(Infineon)
VCTCXO
1XXA26000FBA
(DAISHINKU, 26MHz)
AFC0_DAC
B10
XO
A11
1 VCONT
PAM DCDC
RF6561
(RFMD)
PMU
RF6590
(RFMD)
3 OUT
SP8T, ASM
RF6361A
(RFMD
)
PAM
RF6261B
(RFMD)
CP_OUT
CP_OUT
FB_AM
PA_POW_DET
PA_POW_DET
PA_PAMP
VRAMP
PA_RAMP
RF_OUT
PA_RF
PA_RF
RESET_N
XRESET_N
SYS_CLK
F13
SYS_CLK_EN
F12
REF_CLK_EN
E13
SYS_CLK
P12
SYSCLKEN
U9
K3
REF_CLK_EN
DI3_RX_DAT
C13
DI3_RX_DATX
D13
U7
U8
DI3_RX_DAT
DI3_RX_DATX
DI3_TX_DAT
C12
DI3_TX_DATX
D12
T7
T8
DI3_TX_DAT
DI3_TX_DATX
DI3_SYS_CLK
DI3_SYS_CLK_EN
DI3_REF_CLK_EN
DI3_RX_DAT
DI3_RX_DATX
DI3_TX_DAT
DI3_TX_DATX
5. RF Block Diagram : Control signal and clocks_U2(EU)
B3
CLK_ON
D4
SPI_CLK
B4
SPI_SS
C4
SPI_DRW
K13
CLK_ON
SPI_CLK
SPI_SS
SPI_DRW
14
15
13
SPI_CLK
SPI_EN
SPI_DATA
B4
C5
B5
A6
M12
E3
VSPI
VSPI
16
CLK_ON
SPI_CLK
SPI_SS
SPI_DRW
A4
VSPI
14
VSPI
17
19
VSPI
C1
D1
11
9
10
SPI_CLK
SPI_SS
SPI_DRW
VCMOS
RF Block Diagram : Control signal and clocks_P768