6. BLOCK DIAGRAM
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Copyright © 2012 LG Electronics. Inc. All right reserved.
Only for training and service purposes
LGE Internal Use Only
J1
SIM_CD/GPIO_WK3
RESET_PWRDWN_N
J3
ON1
H2
AH11
HSI2/CAREADY/GPIO164
N
R
E
S
P
W
R
O
N
M
5
AF
7
S
Y
S
_N
R
E
S
W
A
R
M
AE
6
S
Y
S
_N
IR
Q
1
IN
T
K
10
AH
7
S
Y
S
_P
W
R
_R
E
Q
P
R
E
Q
1
J9
AG
9
S
R
_S
C
L
S
R
I2
C
_S
C
L
M
13
AE21
McSPI4_CLK/SDMMC4_CLK/GPIO_151
MIPI_HSI_RX_DATA
N13
F27
UART3_CTS_RCTX/UART1_TX/GPIO_141
USIF1_TXD_MTSR
T3
I2S2_CLK0
N1
AG24
SLIMBUS2_CLOCK/GPIO121
T_OUT0
N4
AH24
SLIMBUS2_DATA/GPIO122
EINT3
K10
AE24
ABE_DMIC_CLK1/GPIO119
EINT1
M9
AF24
ABE_DMIC_DIN1/GPIO120
EINT2
M8
MODEM_SEND
OMAP_SEND
IPC_SRDY
IPC_MRDY
AD
2
S
Y
S
_D
R
M
_M
S
E
C
U
R
E
/G
P
IO
_W
K
6
M
S
E
C
U
R
E
N
2
2. XMM6260 – OMAP Interface / Control signal_U2(EU)
MIPI_HSI_RX_FLG
M14
MIPI_HSI_RX_RDY
L13
McSPI4_SIMO (MIPI_HIS_AC_DATA)
McSPI4_SOMI (MIPI_HIS_AC_FLAG)
McSPI4_CLK (MIPI_HIS_CA_READY)
AF20
McSPI4_SIMO/SDMMC4_CMD/GPIO_152
AF21
McSPI4_SOMI/SDMMC4_DAT0/GPIO_153
RESET_PMU_N
IFX_PWR_ON_SW/
IPC_I2S_SYNC
IPC_I2S_DOUT
IPC_I2S_DIN
IPC_I2S_CLK
I2S2_RX
P1
I2S2_TX
P2
I2S2_WA0
R1
AD27
McSPI2_CLK/GPIO_110
AD25
McSPI2_SIMO/GPIO_112
AD26
McSPI2_SOMI/GPIO_111
AC28
McSPI2_CS0/GPIO_113
USIF1_RXD_MRST
T2
AF23
McSPI1_CS1/UART1_RX/GPIO_138
UART1_TX_IPC
UART1_RX_IPC
UART_TX_IFX
UART_RX_IFX
AF19
HSI1_CAFLAG/McBSP4_FSR/GPIO_86
MIPI_HSI_RX_WAKE
P13
MIPI_HSI_TX_DATA
N12
MIPI_HSI_TX_FLG
L11
MIPI_HSI_AC_WAKE
MIPI_HSI_CA_DATA
AF18
HSI1_ACWAKE/McBSP4_CLKX/GPIO_88
AG19
HSI1_CADATA/McBSP4_CLKR/GPIO_85
AE18
HSI1_CAWAKE/GPIO_84
MIPI_HSI_TX_RDY
M15
MIPI_HSI_TX_WAKE
M13
AE19
HSI1_ACREADY/McBSP4_FSX/GPIO_87
MIPI_HSI_CA_FLAG
MIPI_HSI_AC_READY
MIPI_HSI_CA_WAKE
SR
I2
C
_SC
L
AF
9
S
R
_S
D
A
SR
I2
C
_SD
A
S
R
I2
C
_S
D
A
N
13
AE
28
I2
C
1_
S
C
L
I2
C
1_
SC
L
C
TL
I2
C
_S
C
L
M
4
AE
26
I2
C
1_
S
D
A
I2
C
1_
SD
A
C
TL
I2
C
_S
D
A
N
4
SY
S_
D
R
M
_M
SEC
SYS_
PW
R
R
EQ
SYS_
nI
R
Q
1
SY
S_
nR
ESW
A
R
M
Analog Switch
3 1A
9 2A
2B0 7
1B0 5
AF17
AE17
AG18
XMM6260
OMAP4430
TWL6030
XMM6260 – OMAP Interface / Control signal_P768