3. TECHNICAL BRIEF
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3.10 External memory interface
3.10.1 MSM8255
The memory interface consists of two high-speed, high-performance memory slave interfaces: EBI0 and EBI1;
and one low speed general-purpose/NAND/NOR memory interface: EBI2.
The EBI0 and EBI1 is an external bus interface with support for high-speed 16-bit or 32-bit LPDDR1 and LPDDR2
SDRAM device. The DDR1 target speed is 192 MHz while the DDR2 is at 266 MHz in normal mode.
The EBI2 is an external bus interface with support for the low-speed memory interface. The target frequency is in
the range of less than 80 MHz.
The EBI0 and EBI1 interfaces act as slave devices to all of the bus masters in the MSM device.
They can operate either synchronous or asynchronous to the AXI bus. The masters arbitrate to gain access to the
EBI0 and EBI1. Once access is granted, the selected master issues a transaction to the selected memory interface.
Bus masters are connected to the EBI0 and EBI1 through an AXI bus bridge and communicate according to a 64-
bit, non-blocking AXI bus protocol. The AXI bus bridge provides the arbitration logic for all of the bus masters.
The EBI2 is an external bus interface to support memory devices, such as NAND and asynchronous SRAM, and
peripheral devices, such as the LCD, etc. Both the EBI2 and the NAND flash controllers reside on the 32-bit
peripheral AHB bus.