LG L602i, Руководство по обслуживанию

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3.4 LO Phase-locked Loop
Most LO functions are fully integrated on-chip, do not require user adjustment, and need not be
considered by handset designers. QUALCOMM has established and implemented frequency plans
and LO generation schemes that support the radioOne 6250-IVseries chipset while requiring minimal
off-chip design effort. Only one area requires handset designer attention: the loop filters of each
phase-locked loop (PLL).
3.4.1 UMTS Receiver LO generation
The UMTS Rx LO functional block are distributed between the RFR6202 IC, RTR6250 IC, and
external UMTS_RX_CH_VCO and loop filter components. The external UMTS_RX_CH_VCO must be
enabled for UMTS Rx operation and disabled otherwise; a dedicated MSM6250 IC signal enables the
VCO.
Most UMTS Rx PLL circuits are included within the RTR6250 IC: reference divider, phase detector,
charge pump, feedback divider, and digital logic that generated LOCK status. The buffered 19.2MHz
TCXO signal provides the synthesizer input (REF), the frequency reference to which the PLL is phase
and frequency locked. The reference is divided by the R-Counter to create a fixed frequency input to
the phase detector, FR. The other phase detector input (FV) varies as the loop acquires lock, and is
generated by dividing the RX_VCO_IN frequency using the feedback path’s N-Counter. The closed
loop will force FV to equal FR when locked. If the loop is not locked the error between FV and FR will
create an error signal at the output of the charge pump.
This error signal is filtered by the loop filter and applied to the VCO, tuning the output frequency such
that the error is decreased. Ultimately the loop forces the error to approach zero and the PLL is phase
and the PLL is phase and frequency locked.
Many key PLL performance characteristics are largely determined by the loop filter designstability,
transitory response, settling time, and phase noise.
3. TECHNICAL BRIEF
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Figure 1.4.1-1 UMTS Rx PLL functional block diagram
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