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Block Diagram
66
Low Vcc Detector
A
19
to A
0
A
-1
Address
Latch
X-Decoder
Cell Matrix
Y-Gating
Data Latch
Chip Enable
Output Enable
Logic
Program Voltage
Generator
Erase Voltage
Generator
RY/BY
Buffer
Input/output
Buffer
DQ
15
to DQ
0
State
Control
Command
Register
STB
STB
OE
Y-Decoder
Timer for
program/Erase
CE
WE
Vcc
Vss
RY/BY
BYTE
RESET