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61
Pin Name
Pin No.
I/O
Destination
Function
NMI
4
I
ROMICE
Non-maskable CPU interrupt port (sensed at the falling
edge)
MRSTB 5 I
RESET
IC Master
reset
input
TESTB1
TESTB2
6
8
I
Test
select
TEST0
TEST1
TEST2
TEST3
9
11
12
13
IO
User
test/CPU
general
port
2
Test monitor can be set as the following table by a
register.
T
*
SEL[3:0] TEST0
TEST1
TEST2
TEST3
Remarks
0
Servo monitor 0
Servo monitor 1
Servo monitor 2
Servo monitor 3
1
Data
strobe
0 Data
strobe
1 Data
strobe
2 Data
strobe
3
2
Audio 0
Audio 1
Audio 2
Audio 3
3
DVD
modulation
0 DVD
modulation
1 DVD
modulation
2 DVD
modulation
3
4 DVD-R/CD-R
monitor 0
DVD-R/CD-R
monitor 1
DVD-R/CD-R
monitor 2
DVD-R/CD-R
monitor 3
5 DVD+RW
monitor 0
DVD+RW
monitor 1
DVD+RW
monitor 2
DVD+RW
monitor 3
6
PI/C1 PI/C1 PI/C1 PI/C1
7
PO/C2 PO/C2 PO/C2 PO/C2
8
SLOCK SLOCK SLOCK SLOCK
9
DSYNC DSYNC DSYNC DSYNC
10
CLVCK CLVCK CLVCK CLVCK
11
BLEND BLEND BLEND BLEND
12 SYWINCOR
SYWINCOR
SYWINCOR
SYWINCOR
13
PLL HIGH
PLL HIGH
PLL HIGH
PLL HIGH
14 RAMCON
monitor 0
RAMCON
monitor 1
RAMCOM
monitor 2
RAMCON
monitor 3
15
MIF monitor 0
MIF monitor 1
MIF monitor 2
MIF monitor 3
16 WOBREF
monitor 0
WOBREF
monitor 1
WOBREF
monitor 2
WOBREF
monitor 3
1.4.9 LSI/TEST Control Pin List
* T*SEL can be set for each of pins TEST3, TEST2, TEST1, and TEST0, respectively.