3-8
5. BU2090
• PIN CONFIGURATION
Control circuit
12-bit shift register
Latch
V
SS
2
1
3
4
5
6
7
8
DATA
CLOCK
Q0
Q1
Q2
Q3
Q4
16
15
14
13
12
11
10
9
V
DD
V
SS
2
1
3
DATA
CLOCK
Q0
Q1
Q2
Q3
Q4
V
DD
4
LCK
5
6
7
8
9
10
11
12
13
14
15
16
OE
17
18
Q11
Q10
Q9
Q8
Q7
Q6
Q5
Q11
Q10
Q9
Q8
Q7
Q6
Q5
Output buffer
(open drain)
BU2090 / F / FS
BU2092 / F
Control circuit
Output buffer
(open drain)
12-bit shift register
1
12-bit storage register
V
SS
2
1
3
DATA
CLOCK
Q0
Q1
Q2
Q3
Q4
V
DD
4
LCK
5
6
7
8
9
12
13
14
15
16
17
18
OE
19
20
Q11
Q10
Q9
Q8
Q7
N.C.
N.C.
BU2092FV
Control circuit
Output buffer (open drain)
12-bit shift register
12-bit storage register
Q5
10
11
Q6
• PIN DESCRIPTION
PIN NAME
FUNCTION
TYPE
BU2092/F
BU2090/F/FS
BU2092/FV
1
1
1
DATA
GND
2
2
2
CLOCK
Serial data input
3
3
3
LCK
Data shift clock input
—
4
4
Q0
Data latch clock input
4
5
5
Q1
Parallel data output
5
6
6
Q2
Parallel data output
6
7
7
Q3
Parallel data output
7
8
8
Q4
Parallel data output
8
9
9
Q5
Parallel data output
9
10
10
Q6
Parallel data output
10
11
11
N.C.
Parallel data output
—
—
12
N.C.
Not connected
—
—
13
Q7
Not connected
11
12
14
Q8
Parallel data output
12
13
15
Q9
Parallel data output
13
14
16
Q10
Parallel data output
14
15
17
Q11
Parallel data output
15
16
18
OE
Parallel data output
—
17
19
VSS
Output Enable
16
18
20
VDD
Power supply
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Only for training and service purposes
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