39
Pin No.
Symbol
I/O
Description
38
FE
I
Focus Error input
39
VC
I
Center voltage input
40
VPCO1
O
1, Z, 0
Output of VCO2 charge pump for vari-pitch EFM PLL
41
VCTL
I
Input of VCO2 control voltage for vari-pitch EFM PLL
42
FILO
O
Output of Filter for master PLL (slave=digital PLL)
43
FILI
I
Input of filter for master PLL
44
PCO
O
1, Z,0
Output of charge pump for master PLL
45
CLTV
I
VCO control votage input
46
AVS1
Analog GND
47
RFAC
I
EFM signal input
48
BIAS
I
Asymmetry circuit constant current input
49
ASYI
I
Asymmetry comparator circuit voltage input
50
ASYO
O
1, 0
EFM full-swing output (L=vss, H=VDD)
51
AVD1
Analog power supply (2.5V)
52
VDC1
Digital power supply (2.5V)
53
VDC2
Digital power supply (2.5V)
54
VSC1
Digital GND
55
VSC2
Digital GND
56
FOK
I/O
1, 0
Focus OK input/output
57
MIRR
I/O
1, 0
Mirror signal input/output
58
COUT
I/O
1, 0
Track number count signal input/output
59
GFS
O
1, 0
GFS output
60
SCOR
O
1, 0
“H” when subcode sync S0 or S1 is detected
61
SQSO
O
1, 0
Outputs 80bit Sub Q and 16 bit PCM peak-level data
62
SQCK
I
Clock input for reading SQSO
63
SENS
O
1, Z, 0
SENS output. Sub CPU output
64
SCLK
I
Clock for SENS serial data
65
MUTE
I
“H” for muting. “L” for release.
66
DRVDD
Only D-RAM power supply. Normally GND
67
DRVSS
Only D-RAM GND supply. Normally GND
68
F16M
O
1, 0
1/2 Division of XTLI. Not changes with variable pitch.
69
TESO
O
Test pin. Normally open.
70
MCKO
O
1, 0
Clock output. Inverse output of XTLI
71
VDIO1
Digital power supply (3.3V)
72
VSIO1
Digital GND
73
VSIO2
Digital GND
74
LRCK1
I
LR clock input to DAC (48-bit slot)
75
PCMD1
I
Audio data input to DAC (48-bit slot)
76
BCK1
I
Bit clock input to DAC (48-bit slot)
