IC301 (HD64F3062) : MICOM
Block Diagram
42
Port 3
Address bus
Data bus (upper)
Data bus (lower)
H8/300H CPU
Interrupt controller
ROM
RAM
16-bit timer unit
Programmable
timing pattern
controller (TPC)
8-bit timer unit
(mask ROM or
flash memory)
Cloc
k pulse
Po
rt
6
Po
rt
8
gener
ator
Port 4
Po
rt
5
P5 /A
3
19
RESO/FWE*
ø/P6
7
6
LWR/P6
P4 /D
0
0
P4 /D
1
1
P4 /D
2
2
P4 /D
3
3
P4 /D
4
4
P4 /D
5
5
P4 /D
6
6
P4 /D
7
7
P3 /D
0
8
P3 /D
1
9
P3 /D
2
10
P3 /D
3
11
P3 /D
4
12
P3 /D
5
13
P3 /D
6
14
P3 /D
7
15
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
CC
V
CC
V
CC
MD
2
MD
1
MD
0
EXTAL
XTAL
STBY
P5 /A
2
18
P5 /A
1
17
P5 /A
0
16
Po
rt
9
P9 /SCK /IRQ
5
1
5
P9 /SCK
4
0
P9 /RxD
3
1
P9 /RxD
2
0
P9 /TxD
1
1
P9 /TxD
0
0
Po
rt
2
P2 /A
7
15
P2 /A
6
14
P2 /A
5
13
P2 /A
4
12
P2 /A
3
11
P2 /A
2
10
P2 /A
1
9
P2 /A
0
8
Po
rt
1
P1 /A
7
7
P1 /A
6
6
P1 /A
5
5
P1 /A
4
4
P1 /A
3
3
P1 /A
2
2
P1 /A
1
1
P1 /A
0
0
/IRQ
4
Bus controller
Watchdog timer
Serial communication
interface
(SCI) x 2 channels
A/D converter
D/A converter
(WDT)
RES
NMI
5
HWR/P6
4
RD/P6
3
AS/P6
2
BACK/P6
1
BREQ/P6
0
WAIT/P6
4
0
CS /P8
3
3
1
ADTRG/CS /IRQ /P8
2
2
2
CS /IRQ /P8
1
1
3
CS /IRQ /P8
0
0
IRQ /P8
7
15
TP /PB
6
14
TP /PB
5
13
TP /PB
4
12
TP /PB
3
11
3
4
CS /TMIO /TP /PB
2
10
2
5
CS /TMO /TP /PB
1
9
1
6
CS /TMIO /TP /PB
0
8
0
7
CS /TMO /TP /PB
7
7
2
20
A /TIOCB /TP /P
A
6
6
2
21
5
5
1
22
4
4
1
23
A /TIOCA /TP /P
A
A /TICOB /TP /P
A
A /TICO
A /TP /P
A
3
3
0
TCLKD/TIOCB /TP /P
A
2
2
0
TCLKC/TIOCA /TP /P
A
1
1
00
TCLKB/TP /P
A
TCLKA/TP /P
A
77
1
D
A
/AN /P7
66
0
D
A
/AN /P7
55
AN /P7
44
AN /P7
33
AN /P7
22
AN /P7
11
AN /P7
00
AN /P7
REF
V
CC
AV
SS
AV
Port A
Port 7
Port B
* Functions as RESO in the mask ROM versions and as FWE in the flash memory version.