LG AR140B, Руководство по обслуживанию

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8. CIRCUIT DIAGRAM
LGE Internal Use Only Copyright © 2009 LG Electronics. Inc. All right reserved.
Only for training and service purposes
L
K
J
I
H
G
F
E
D
C
B
A
12 11 10 9 8 7 6 5 4 3 2 1
L
K
J
I
H
G
F
E
D
C
B
A
12 11 10 9 8 7 6 5 4 3 2 1
VBAT
0
0
1
CU
1
0.
0
0
0
1
RR
1
2V9_VMME
1
0
1
CP
9
3
1V35_CORE
R
0
1
0 1
R
U
1
2
0
1
C
P
9
3
3
0
1
C
1V8_SD
2
0
1
R
K 5.
1
1V35_VPLL
VBAT
0
0
1
B
F
1
0
1
B
F
4
0
1
Cn
0
0
1
U
1.
0
5
0
1
C
U
1.
0
6
0
1
C
P
9
3
7
0
1
C
R103
1K
2V62_VIO
U
1.
0
8
0
1
C
9
0
1
CU
1
0.
0
2V62_VIO
0
1
1
CU
1
3.3K
R104
U
1.
0
1 1
1
C
U
1.
0
2 1
1
C
TP100
390K
R105
2
0
1
B
F
U
1.
0
3
1
1
C
4
1
1
CP
9
3
5 1
1
Cn
0
0
1
22K
R106
TP101
x
220N C116
U
1
7
1
1
C
2V85_CAM
K 5.
1
7
0
1
R
TP102
1V8_SD
8 1
1
CU
1.
0
9
1
1
CU
1
0
2
1
CU
1.
0
C121
22P
U
1.
0
2
2
1
C
3
2
1
Cn
0
0
1
10K
R108
1V8_SD
TP103
4
2
1
CU
1.
0
5
2
1
CU
1.
0
2V62_VIO
2V9_SIM
TP104
6
2
1
C
n 0
0
1
7
2
1
CU
1.
0
CN100
AXT430124
ENBY0029001
16 15
17 14
18 13
19 12
20 11
21 10
22 9
23 8
24 7
25 6
26 5
27 4
28 3
29 2
30 1
G1 G2
G3 G4
DNI
R109
8
2
1
CU
1.
0
TP105
R110
10K
9
2
1
CU
1.
0
2V62_VIO
100K
R111
VBUS_USB
2V11_RTC
0
3
1
Cn
0
0
1
1V8_SD
2V62_VIO
1V8_SD
1 3
1
CU
1.
0
2V5_VAUDA
2
3
1
Cn
1
3
3
1
CU
1.
0
3
0
1
B
F
TP106
5 1
F
9 1
C
3 1
Y
7 1
A
4 1
C
7 1
G
9 1
F
9 1
E
8 1
F
5 1
G
9 1
G
9 1
B
7 1
E
8 1
E
9 1
D
6 1
E
6 1
U
5 1
T
6 1
L
8 1
L
9 1
L
9 1
M
7 1
L
7 1
M
8 1
M
9 1
P
9 1
N
9 1
V
8 1
V
9 1
U
8 1
U
9 1
T
8 1
T
PMB8877
U101
6 E 1 K 4 H 4 E 2 E 3 E 4 1
F
6 1
G
6 1
J
9 1
H
4 F 1 E 3 F 5 F 9 1
R
8 1
R
8 1
P
7 1
P
5 G 1 F 3 G 4 G 3 K 1 J 2 J 5 H 3 H 5 J 1 G 0 1
A
6 A 6 B 4 A 9 E 7 B 8 E 8 A 9 B 8 B 8 C 9 A 1 1
A
9 F 7 C 8 F 1 D 4 C 1 B 3 C 5 C 5 E 1 C 2 C 4 B 3 B 2 A 3 A 7 E 5 B 6 C 7 F
Y8
G18 T10
H17 Y9
J19 U11
J18 AA7
C10
R15 B16
R16 E14
Y14
H18 F16
W14 F13
AA15 C16
AA16 C15
B18
U10 A18
W8
Y7 G2
F2
Y4
U5 W11
V3 F6
AA2 D2
Y2 D3
Y3 A14
W3 F10
C9
R3 B11
L1 A12
M1 E10
K2
K17
T11 K18
H16
T5
T6 H15
U4 U12
U3 W12
N4 C18
N3
P3 B17
R2 E15
D18
P4 D17
M4
M5
R1
L4
K5
K4
J4
N2 C13
P2 B15
N1 B12
M3 C12
L5 E12
J3 C11
L3 B13
M2 F12
E11
T4 A15
T3 F11
P5 B14
T2 E13
R4
T1 K15
R5 M16
W2 M15
U2 N15
N5 M12
V1 K16
W9
U9 U15
Y6 Y16
W7 AA17
T9 W16
W6 Y17
AA5 AA18
Y5 W17
U7 Y18
T7 Y19
AA4 V17
W5 W18
U6
T8
W4
U8
2
1
Y
1
1
Y
5
1
Y
9
A
A
1
1
A
A
2
1
A
A
0
1
Y
8
A
A
7
1
N
8
1
N
7
1
U
9
1
W
7
1
R
7
1
T
5
1
J
6
1
N
6
1
P
4
1
U
3
1
T
5
1
W
3
1
U
4
1
T
6
1
T
5
1
L
5
1
P
2
L
2
1
T
3
1
W
4
1
A
A
3
1
A
A
9
1
K
3
1
A
0
1
B
1
H
7
1
J
2
H
7
A
2
B
7
1
C
6
1
A
5
A
7
1
F
0
1
W
1
W
2
V
1
U
1
P
1
Y
6
A
A
3
A
A
0
1
A
A
8
M
9
M
0
1
M
1
1
M
8
K
9
K
0
1
K
1
1
K
2
1
K
9
N
0
1
N
8
L
9
L
0
1
L
1
1
L
2
1
L
9
J
0
1
J
1
1
J
1
1
N
9
1
A
A
1
A
A
9
1
A
1
A
1
A
_ R
E
N
R
O C
2
A
_ R
E
N
R
O C
1
A
A _
R
E
N R
O
C
2
A
A _
R
E
N R
O
C
C
N
1
NI
A
M
_ D
D
V
2
NI
A
M
_ D
D
V
3
NI
A
M
_ D
D
V
4
NI
A
M
_ D
D
V
5
NI
A
M
_ D
D
V
6
NI
A
M
_ D
D
V
7
NI
A
M
_ D
D
V
8
NI
A
M
_ D
D
V
9
NI
A
M
_ D
D
V
0
1
NI
A
M _
D
D
V
1
NI
A
M
_ S
S
V
2
NI
A
M
_ S
S
V
3
NI
A
M
_ S
S
V
4
NI
A
M
_ S
S
V
5
NI
A
M
_ S
S
V
6
NI
A
M
_ S
S
V
7
NI
A
M
_ S
S
V
8
NI
A
M
_ S
S
V
9
NI
A
M
_ S
S
V
1
M
T
E _
M
E
M _
P
D
D V
2
M
T
E _
M
E
M _
P
D
D V
3
M
T
E _
M
E
M _
P
D
D V
4
M
T
E _
M
E
M _
P
D
D V
5
M
T
E _
M
E
M _
P
D
D V
1
M
T
E _
M
E
M _
P
S
S V
2
M
T
E _
M
E
M _
P
S
S V
3
M
T
E _
M
E
M _
P
S
S V
4
M
T
E _
M
E
M _
P
S
S V
A
GI
D
_
P D
D
V
B
GI
D
_
P D
D
V
1
C
GI
D
_ P
D
D
V
2
C
GI
D
_ P
D
D
V
D
GI
D
_
P
D D
V
2
GI
D
_
P S
S
V
1
GI
D
_
P S
S
V
3
GI
D
_
P S
S
V
E
GI
D
_
P D
D
V
4
GI
D
_
P S
S
V
C
M
M
_
P D
D
V
MI
S _
P
D
D V
C
T
R _
D
D
V
C
T
R _
S
S
V
L
L
P _
D
D
V
L
L
P _
S
S V
S
F
_ E
S
U
F _
D
D
V
B
B
_ A
D
D
V
B
B
_ A
S
S
V
D
_
A
D D
V
D
_
A S
S
V
M
_
A
D D
V
M
_
A
S S
V
G
B
_
A D
D
V
G
B
_
A S
S
V
N
F
E
R V
D
N
G
A
D
R
A
U
G
1
R
B V
_
A
D D
V
1
R
B V
_
A
S S
V
2
R
B V
_
A
D D
V
2
R
B V
_
A
S S
V
T
B
V _
A
D
D V
T
B
V _
A
S
S V
0
T
K P
E
C
A R
T
1
T
K P
E
C
A R
T
2
T
K P
E
C
A R
T
3
T
K P
E
C
A R
T
4
T
K P
E
C
A R
T
5
T
K P
E
C
A R
T
6
T
K P
E
C
A R
T
7
T
K P
E
C
A R
T MEM_A0
MEM_A1
MEM_A2
MEM_A3
M_0 MEM_A4
M_1 MEM_A5
M_2 MEM_A6
M_3 MEM_A7
M_4 MEM_A8
M_5 MEM_A9
M_6 MEM_A10
M_7 MEM_A11
M_8 MEM_A12
M_9 MEM_A13
M_10 MEM_A14
MEM_A15
PAOUT11 MEM_A16
PAOUT12 MEM_A17
BB_I MEM_A18
BB_IX MEM_A19
BB_Q MEM_A20
BB_QX MEM_A21
MEM_A22
T_OUT0 MEM_A23
T_OUT1 MEM_A24
T_OUT2 MEM_A25
T_OUT3 MEM_A26
T_OUT4
T_OUT5 MEM_AD0
T_OUT6 MEM_AD1
T_OUT7 MEM_AD2
T_OUT8 MEM_AD3
T_OUT9 MEM_AD4
T_OUT10 MEM_AD5
T_IN0 MEM_AD6
T_IN1 MEM_AD7
MEM_AD8
MEM_AD9
MEM_AD10
MEM_AD11
MEM_AD12
MEM_AD13
MEM_AD14
RF_STR0 MEM_AD15
RF_STR1
RF_DATA MEM_CS0_N
RF_CLK MEM_CS1_N
MEM_CS2_N
AFC MEM_CS3_N
CLKOUT0 MEM_CSA0_N
F26M MEM_CSA1_N
SWIF_TXRX MEM_CSA2_N
MEM_CSA3_N
CC_IO
CC_CLK FCDP_RBN
CC_RST
MEM_WAITN
MMCI1_CMD MEM_ADVN
MMCI1_CLK MEM_RDN
MMCI1_DAT0 MEM_WRN
MMCI1_DAT1
MMCI1_DAT2 MEM_BFCLKO1
MMCI1_DAT3 MEM_BFCLKO2
MMCI2_CMD MEM_SDCLKO
MMCI2_DAT0 MEM_BC0_N
MMCI2_CLK MEM_BC1_N
FWP MEM_BC2_N
MEM_BC3_N
IRDA_TX
IRDA_RX MEM_RAS_N
MEM_CAS_N
TDO MEM_CKE
TDI
TMS F32K
TCK OSC32K
TRST_N RESET_N
RTCK RSTOUT_N
RTC_OUT
TRIG_IN VREFP
MON1 IREF
MON2
TRACESYNC SPCU_RQ_IN0
TRACECLK SPCU_RQ_IN1
PIPESTAT2 SPCU_RC_OUT0
PIPESTAT1 SPCU_RQ_IN2
PIPESTAT0
0
D
_ FI
D
1
D
_ FI
D
2
D
_ FI
D
3
D
_ FI
D
4
D
_ FI
D
5
D
_ FI
D
6
D
_ FI
D
7
D
_ FI
D
8
D
_ FI
D
1
S
C
_ FI
D
2
S
C
_ FI
D
D
C
_ FI
D
R
W
_ FI
D
D
R
_ FI
D
D
H
_ FI
D
D
V
_ FI
D
1
T
E S
E
R
_ FI
D
2
T
E S
E
R
_ FI
D
0
D
_ FI
C
1
D
_ FI
C
2
D
_ FI
C
3
D
_ FI
C
4
D
_ FI
C
5
D
_ FI
C
6
D
_ FI
C
7
D
_ FI
C
K L
C
P
_ FI
C
C
N Y
S
H
_ FI
C
C
N
Y S
V
_ FI
C
2
T U
O
K
L C
D
P
_ FI
C
T
E S
E
R
_ FI
C
0
NI
_
P K
1
NI
_
P K
2
NI
_
P K
3
NI
_
P K
4
NI
_
P K
5
NI
_
P K
6
NI
_
P K
0
T U
O
_
P K
1
T U
O
_
P K
2
T U
O
_
P K
3
T U
O
_
P K
1
1
N
P E
2
1
N
P E
1 1
P
P E
2 1
P
P E
1 1
A
P
P E
2 1
A
P
P E
1 F
E
R
P E
2 F
E
R
P E
1 2
A
P
P E
2 2
A
P
P E
1 N
CI
M
1 P
CI
M
2 N
CI
M
2 P
CI
M
1
N
X
U A
1
P
X
U A
2
N
X
U A
2
P
X
U A
D
N
G
X
U A
P CI
M V
N CI
M V
0
K
L C
_
1 S
2I
1
K
L C
_
1 S
2I
X R
_
1 S
2I
X T
_
1 S
2I
0 A
W
_
1 S
2I
0
K
L C
_
2 S
2I
1
K
L C
_
2 S
2I
X R
_
2 S
2I
X T
_
2 S
2I
0 A
W
_
2 S
2I
1 A
W
_
2 S
2I
L
C S
_
1 C
2I
A
D S
_
1 C
2I
T
NI
_
M P
L
C S
_
2 C
2I
A
D S
_
2 C
2I
T
S
R
M _
D
X
R _
1
FI
S U
R
S
T
M _
D
X
T _
1
FI
S U
N _
S
T
R _
1
FI
S U
N _
S
T
C _
1
FI
S U
T
S
R
M _
D
X
R _
2
FI
S U
R
S
T
M _
D
X
T _
2
FI
S U
N _
S
T
R _
2
FI
S U
N _
S
T
C _
2
FI
S U
T
S
R
M _
D
X
R _
3
FI
S U
R
S
T
M _
D
X
T _
3
FI
S U
K
L
C
S _
3
FI
S U
0
NI
P
S D
1
NI
P
S D
1 T
U
O
P
S D
R112
1K
OJ100
1V8_SD
U
1.
0
4
3
1
C
22P
C135
6
3
1
CU
1
U
1.
0
7
3
1
C
OJ101
UT100
12
11
10
9
8
7
6
5
4
3
2
1
GND
RX
TX
NC1
ON_SW
VBAT
NC2
NC3
NC4
DSR
RTS
CTS
GND
RX
TX
VCHAR
ON_SW
VBAT
PWR
URXD
UTXD
3G 2.5G
2V5_VAUDB
C138
0.1U
TP107
TOUT100
9
3
1
CU
1.
0
32.768KHZ
X100 2 1
1V8_SD
0
4
1
Cn
0
0
1
K5E1H12ACB-A075
EUSY0335806
U100
9 N 2 N 6 H 5 H 6 G 5 G 5 F 6 D 6 E 5 E 5 C 5 D 4 G 6 C
J3 M8
F3 K8
M7
K7
N8 M6
N5 K6
B5 M5
K5
L8
N6 J8
L7
N7 J7
B6 L6
J6
L5
L2 J5
J2
E2
H3
N4 G3
G2 F7
F9 E7
C2 D8
D7
F8
K2 G8
F2 H4
D2
E9
M2
H2
G9 N3
B4 M4
M3
L4
G7 L3
H9 K4
D9 K3
H8 J4
H7 F4
J9 E3
K9 E4
L9 D3
M9 D4
B8 C3
C9 C4
C8 B3
C7
6
F
8
E
9
B
7
B
2
B
0 1
P
9
P
2
P
1
P
0 1
N
1
N
0 1
B
1
B
0 1
A
9
A
2
A
1
U
N
D
2
U
N
D
3
U
N
D
4
U
N
D
5
U
N
D
6
U
N
D
7
U
N
D
8
U
N
D
9
U
N
D
0
1
U N
D
1
1
U N
D
1
C
N
2
C
N
3
C
N
4
C
N
5
C
N
A0
DQ0 A1
DQ1 A2
DQ2 A3
DQ3 A4
DQ4 A5
DQ5 A6
DQ6 A7
DQ7 A8
DQ8 A9
DQ9 A10
DQ10 A11
DQ11 A12
DQ12
DQ13
DQ14 VDD1
DQ15 VDD2
VDD3
VDD4
_CS
VDDQ1
CLK VDDQ2
CKE VDDQ3
_WED
BA0
BA1 VSS1
_RAS VSS2
_CAS VSS3
LDQM VSS4
UDQM
VSSQ1
VSSQ2
IO0 VSSQ3
IO1
IO2
IO3 VCC1
IO4 VCC2
IO5
IO6 VCCQ
IO7
IO8
IO9 VSS5
IO10 VSS6
IO11 VSS7
IO12
IO13
IO14 LDQS
IO15 UDQS
E
C _
K
C _
E
L A
E
L C
E
R _
B
_
_ R
E
W
_
P
W
_
6
C N
7
C N
8
C N
9
C N
0
1
C N
1
1
C N
R115
DNI 10K
R116
R113
10k DNI
R114
T
NI
_
CI
U
M
T
NI
_
D
E
L
P _
CI
M
_
NI
A
M
P _
CI
M
_
S
H
N _
CI
M
_
S
H
N _
CI
M
_
NI
A
M
P _
CI
M
V
LED_CNT
T E
S
E
R
_
D
E
L
_
FLIP
USB_DP
USB_DM
DATA[15]
DATA[15]
DATA[13]
DATA[13]
DATA[9]
DATA[9]
DATA[8]
DATA[8]
DATA[7]
DATA[7]
DATA[6]
DATA[6]
DATA[5]
DATA[5]
DATA[4]
DATA[4]
DATA[3]
DATA[3]
DATA[2]
DATA[2]
BT_LDO_EN
K L
C
_
1
S
2I
T
C E
T
E
D
_
C
M
M
KEY_ROW5
DBB_INT
PA_LEVEL
UDQS
UDQS
LDQS
LDQS
ADD[30]
ADD[30]
ADD[29]
ADD[29]
TRIG_IN
TRIG_IN
EXTRSTN
R _
D
N
S
_
B
B
A
D S
_
FI
C
L
C
S
_
FI
C
S T
R
_
T
B
_
T
R
A
U
S T
C
_
T
B
_
T
R
A
U
K
L
C
M
_
FI
C
M
V
_ 0
E
S
_
B
S
U
VIB_EN
MMC_D[3]
MMC_D[0]
MMC_CMD
MMC_CLK
SDCLKI
SDCLKI
N
E _
Y
E
K
G
O
D
W
KEY_COL3
KEY_COL0
KEY_ROW3
KEY_ROW2
KEY_ROW4
KEY_ROW1
KEY_COL1
DI
_
D
C
L
KEY_COL2
KEY_ROW0
USB_OEN
C
N
Y
S
V
_
FI
C
T
E
S
E
R
_ FI
C
D
P
_
FI
C
K
L
C
P
_ FI
C
C
N
Y
S
H
_
FI
C
KEY_COL4
R
P
P _
K 2
3
K
L
C
_CHG_EN
C
N
Y
S
V
_
FI
D
SDCLKO
SDCLKO
N
F
E
R
V
VREFN
N
E _
O
X
C
V
MMC_D[1]
MMC_D[2]
X T
_
T
B
_
T
R
A
U
X
R _
T
B
_
T
R
A
U
PA_MODE
FE1
PA_BAND
TXON_PA
TRSTN
TRSTN
TRACESYNC
TRACESYNC
7
T
K
P
E
C
A
R
T
TRACEPKT7
6
T
K
P
E
C
A
R
T
TRACEPKT6
5
T
K
P
E
C
A
R
T
TRACEPKT5
4
T
K
P
E
C
A
R
T
TRACEPKT4
3
T
K
P
E
C
A
R
T
TRACEPKT3
2
T
K
P
E
C
A
R
T
TRACEPKT2
1
T
K
P
E
C
A
R
T
TRACEPKT1
0
T
K
P
E
C
A
R
T
TRACEPKT0
TRACECLK
TRACECLK
TMS
TMS
TDO
TDO
TDI
TDI
TCK
TCK
A
D
S
L
C
S
FE2
RTC_OUT
RTCK
RTCK
RF_EN
RF_DA
RF_CLK
_RESET
T
NI
_
M
P
PIPESTAT2
PIPESTAT2
PIPESTAT1
PIPESTAT1
PIPESTAT0
PIPESTAT0
RF_TEMP
BAT_ID
C
O
E _
0
A
W
_
1
S
2I
X T
_
1
S
2I
X
R _
1
S
2I
26MHZ_MCLK
L
_
D
N
S
_
B
B
P _
R
A
E
N _
R
A
E
_WR
_WR
_WR
_RD
_RD
_RAM_CS
_RAM_CS
CKE
CKE
_CAS
_CAS
FCDP
FCDP
_BC1
_BC1
_BC0
_BC0
_NAND_CS
_NAND_CS
ADD[4]
ADD[4]
ADD[3]
ADD[3]
ADD[2]
ADD[2]
DATA[0]
DATA[0]
ADD[15]
ADD[15]
ADD[9]
ADD[9]
ADD[14]
ADD[14]
ADD[8]
ADD[8]
ADD[13]
ADD[13]
ADD[7]
ADD[7]
ADD[12]
ADD[12]
ADD[6]
ADD[6]
ADD[11]
ADD[11]
ADD[5]
ADD[5]
ADD[10]
ADD[10]
ADD[1]
ADD[1]
ADD[0]
ADD[0]
P
V _
T
A
D
_
B
S
U
R
W
_
FI
D
_
T
E
S
E
R
_ FI
D
_
7
D
_
FI
D
6
D
_
FI
D
5
D
_
FI
D
4
D
_
FI
D
2
D
_
FI
D
1
D
_
FI
D
0
D
_
FI
D
S
C
_
NI
A
M
_
FI
D
D
C
_
FI
D
D
R
_
FI
D 7
D
_
FI
C
6
D
_
FI
C
5
D
_
FI
C
4
D
_
FI
C
3
D
_
FI
C
2
D
_
FI
C
1
D
_
FI
C
0
D
_
FI
C
SIM_RST
SIM_IO
SIM_CLK
QX
Q
IX
I
_RAS
_RAS
N
T E
S
E
R
_
T
B
L
R
T
C
_
E
C
R
U
O
S
E
R
UART_TX
X T
_
T
R
A
U
UART_RX
X
R _
T
R
A
U
N _
CI
M
V
3
D
_
FI
D
T
NI
_
T B
RPWRON
RPWRON
N
E _
O
D L
_
M
A
C
LCD_BACKLIGHT_EN
DATA[10]
DATA[10]
DATA[11]
DATA[11]
ADD[16]
ADD[16]
ADD[16]
ADD[17]
ADD[17]
ADD[17]
ADD[18]
ADD[18]
ADD[19]
ADD[19]
ADD[20]
ADD[20]
ADD[21]
ADD[21]
ADD[22]
ADD[22]
ADD[23]
ADD[23]
ADD[24]
ADD[24]
ADD[25]
ADD[25]
ADD[26]
ADD[26]
ADD[27]
ADD[27]
ADD[28]
ADD[28]
DATA[14]
DATA[14]
DATA[12]
DATA[12]
DATA[1]
DATA[1]
1
FI
_
D
C
L
2
FI
_
D
C
L
DSR
DSR
ADD[16:28]
ADD[0:15]
ADD[0:26]
(1%)
BASE BAND PROCESSOR
Large Block : R109 -> NA, R103 -> 1K
1G NAND(Large Block x16bit) +512M DDR SDRAM
ON BOARD ARM9 JTAG & ETM INTERFACE
PCB Version
D2 D3
L L
L H
H L
(1%)
UART
(1%)
Small Block : R109 -> 10K, R103 -> NA
H H
Version
C
1.0
1.1
1.2
Boot Mode