LG AR140B, Руководство по обслуживанию

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3. Technical Brief
3.6. Memory
1Gbit Flash & 512Mbit DDRAM employed on GD310 with 8 & 16 bit parallel data bus thru ADD(0) ~
ADD(26). The 1Gbit Nand Flash memory with DDRAM stacked device family offers multiple
high-performance solutions.
Figure 10. Flash memory & DDR RAM MCP circuit diagram
1V8_SD
U
1.
0
5
0
1
C
U
1.
0
6
0
1
C
U
1.
0
8
0
1
C
3.3K
R104
U
1.
0
3
1
1
C
TP101
x
10K
R108
4
2
1
CU
1.
0
TP104
8
2
1
CU
1.
0
1V8_SD
1V8_SD
3
3
1
CU
1.
0
TP106
U
1.
0
7
3
1
C
1V8_SD
K5E1H12ACB-A075
EUSY0335806
U100
9
N
2
N
6
H
5
H
6
G
5
G
5
F
6
D
6
E
5
E
5
C
5
D
4
G
6
C
J3 M8
F3 K8
M7
K7
N8 M6
N5 K6
B5 M5
K5
L8
N6 J8
L7
N7 J7
B6 L6
J6
L5
L2 J5
J2
E2
H3
N4 G3
G2 F7
F9 E7
C2 D8
D7
F8
K2 G8
F2 H4
D2
E9
M2
H2
G9 N3
B4 M4
M3
L4
G7 L3
H9 K4
D9 K3
H8 J4
H7 F4
J9 E3
K9 E4
L9 D3
M9 D4
B8 C3
C9 C4
C8 B3
C7
6
F
8
E
9
B
7
B
2
B
0
1
P
9
P
2
P
1
P
0
1
N
1
N
0
1
B
1
B
0
1
A
9
A
2
A
1
U
N
D
2
U
N
D
3
U
N
D
4
U
N
D
5
U
N
D
6
U
N
D
7
U
N
D
8
U
N
D
9
U
N
D
0
1
U
N
D
1
1
U
N
D
1
C
N
2
C
N
3
C
N
4
C
N
5
C
N
A0
DQ0 A1
DQ1 A2
DQ2 A3
DQ3 A4
DQ4 A5
DQ5 A6
DQ6 A7
DQ7 A8
DQ8 A9
DQ9 A10
DQ10 A11
DQ11 A12
DQ12
DQ13
DQ14 VDD1
DQ15 VDD2
VDD3
VDD4
_CS
VDDQ1
CLK VDDQ2
CKE VDDQ3
_WED
BA0
BA1 VSS1
_RAS VSS2
_CAS VSS3
LDQM VSS4
UDQM
VSSQ1
VSSQ2
IO0 VSSQ3
IO1
IO2
IO3 VCC1
IO4 VCC2
IO5
IO6 VCCQ
IO7
IO8
IO9 VSS5
IO10 VSS6
IO11 VSS7
IO12
IO13
IO14 LDQS
IO15 UDQS
E
C
_
K
C
_
E
L
A
E
L
C
E
R
_
B
_
_
R
E
W
_
P
W
_
6
C
N
7
C
N
8
C
N
9
C
N
0
1
C
N
1
1
C
N
DATA[15]
DATA[13]
DATA[9]
DATA[8]
DATA[7]
DATA[6]
DATA[5]
DATA[4]
DATA[3]
DATA[2]
UDQS
LDQS
ADD[30]
ADD[29]
SDCLKI
SDCLKO
_WR
_WR
_RD
_RAM_CS
CKE
_CAS
FCDP
_BC1
_BC0
_NAND_CS
ADD[4]
ADD[3]
ADD[2]
DATA[0]
ADD[15]
ADD[9]
ADD[14]
ADD[8]
ADD[13]
ADD[7]
ADD[12]
ADD[6]
ADD[11]
ADD[5]
ADD[10]
ADD[1]
ADD[0]
_RAS
DATA[10]
DATA[11]
ADD[16]
ADD[16]
ADD[17]
ADD[17]
ADD[18]
ADD[19]
ADD[20]
ADD[21]
ADD[22]
ADD[23]
ADD[24]
ADD[25]
ADD[26]
ADD[27]
ADD[28]
DATA[14]
DATA[12]
DATA[1]
ADD[16:28]
ADD[0:15]