Lexicon CORE2, Руководство по обслуживанию

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Lexicon Studio Core2 Service Manual
6-8
Audio I/O & Connectors (schematic sheet 5.)
The S/PDIF serial output signal (SPDIG_OUT) is buffered by U22 and AC coupled to become the
SPDIF_OUT signal which is sent to the connector box. The AC coupled SPDIF_IN signal is buffered and
amplified by U28 which presents the SPDIG_IN signal to the FPGA. The SPDIF input on the Core2 can
also accept a TTL wordclock signal to synchronize the Core2 to an external wordclock source. CP1 is the
optical receiver for ADAT data, and it may also be used to receive optical SPDIF data. CP2 is the optical
transmitter for ADAT data, and it may also be used to transmit optical S/PDIF data.
A/D Conversion (schematic sheet 6.)
The following description applies to the first A/D conversion channel. The other three channels work in
exactly the same manner. The single-ended analog audio input is received as CH1_IN, scaled by R9 and
R13, and buffered by U1 (4580). The buffered input is then sent to the Input Level Control (U3). The gain of
the output of this device (AOUTL) is controlled by software. The serial control interface of this device is the
signals ADVC_CLK, ADVC_SDIN, and ADVC12_CS/.
The next element in the analog chain is the dBx type 4 tape saturation emulation. Pre-emphasis is applied
using R73, C74, and R72. This pre-emphasis is always active even if the dBx type 4 jumpers are disabled.
Software running on the DSP56301 performs the corresponding de-emphasis. Jumpers labeled “IN” and
“OUT” are used to select if dBx type 4 is enabled or disabled. When the jumper is in position “IN” it is
enabled, and when it is in position “OUT” it is disabled. The ADSAT1 signal is a means for the DSP56301 to
detect the position of the jumper. When the jumper is in the “IN” position the dual diode packs D1 and D2
are used to create the soft-knee compression. When the signal is sufficiently large D2 and R85 shape the
positive excursions while D1 and R84 shape the negative excursions. U13 is an inverting stage that
provides a summing node for the dBx type 4 function.
At this point the signal is AC coupled (C84) to become the negative leg of the differential input to the
AK5383 A/D converter (U17). The AK5383 requires differential drive, 2.5 Vpp per pin, biased at 2.5V. U15
develops the differential drive for the converter with bias provided by R93 and R92. The Bias voltage is
filtered by C83 and C82. R105 and R104 provide op amp stability, and C100 decreases the clock feed-
through noise of the AK5393 modulator. The A/D converter delivers 24 bit I2S format serial digital audio the
DSP56301.
D/A Conversion (schematic sheets 8, 9 )
The following description applies to the first D/A conversion channel. The other seven channels work in
exactly the same manner. The AK4324 D/A converter (U9) accepts 24 bit I2S data from the DSP56301.
The differential outputs of the converter are 2.8 Vpp per pin centered around 2.5V. These differential
outputs are summed and buffered using U5 (4580). The output filters formed by R19, R21-25, and C15-18
are used to reject noise beyond the audio passband.
Voltage Regulators (schematic sheet 10.)
U26 is a 3.3V regulator used to power the DSP56301 and the digital interface portions of the A/D
converters. The power s3VD and +3VA are actually 3.3V. U20 is a +5V regulator used to supply
quiet +5V power to the analog components on Core2. The series diodes D15-D20 are used to dissipate
power to lessen the power dissipation requirements of U20. U19 is a –5V regulator used to supply power as
required by the CS3310 volume control I.C.s.