DC Inverter Multi VRF System
24
5.2.2 Test Operation and Debugging
Description of test operation procedures and main board display of ODU.
VEPS075N432K
,
VEPS096N432K
,
VEPS120N432K
:
Description of each stage of debugging progress
——
Debugging code
Code meaning and operation method
Progress
LED
Code
Display status
01_Set master unit
A0
ON
System is not debugged, hold main board’s SW3 button for 5s
to start debugging.
01
ON
2s later, next step starts.
02_ Allocate
addresses
02/Ad
Display
circularly
System is allocating addresses. 10s later, display as below:
02/L7
Display
circularly
No master indoor unit. Display will be on for 1min, during
which master IDU can be set manually. If not, system will set
the unit with minimum IP address as the master IDU.
02/oC
Display
circularly
Allocation is finished. 2s later, next step starts.
03_ Confirm the
quantity of ODU
03/01
Display
circularly
System is confirming. 1s later, next step starts.
Содержание VEPS075N432K
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