30
bit 14, 15
Read only, indicates the program load in use. Common
Stop Double Word mode is 2
control register 1 (subaddress 1)
bits 0-3
Selects the trigger output pulse width, in clock units, 0 to
15. Default is 0.
bits 4-7
Selects the trigger pulse delay, in clock units. The
maximum delay is 15 clock units. Default is 0.
bits 8-9
Selects the trigger clock unit.
0 = 25 nsec (default)
1 = 50 nsec
2 = 100 nsec
3 = selects external trigger clock
bit 10-11
Selects the Measure Pause Interval (MPI).
0 = no MPI (default)
1 = 800 nsec MPI
2 = 1600 nsec MPI
3 = 3200 nsec MPI
bit 12
Selects FAST FERA mode; 1=fast 0=normal (default)
bit 13 - 15
Event serial number. This 3 bit number is in the header
data word. It is incremented after each event. It can be
written and read to allow synchronizing several modules.
It is cleared by CAMAC command F9. Default is 0.
control register 2 (subaddress 2)
bits 0-3
The maximum number of hits allowed per TDC channel,
from 1 to 16. A value of zero selects 16 hits. Default is 15.
bits 4-15
The maximum full scale time allowed for the TDC data, in
units of 8 nsec, from 0 to 32767.5 nsec. Bit 4 has a value
of 8 nsec.
control register 3 (subaddress 3)
bits 0-3
The request delay setting. This is used only in 4300B
FERA ADC compatible mode. The range is from 0 to
30 microseconds, in 2 microsecond steps. In this mode
the BUSY output becomes the FERA REQUEST output.
Default is 0.
bits 4-15
Not used, always read 0.
A simple example of Common STOP register setup
0 = 10FFH
buffered mode, CAMAC readout, leading edge only,
header always, module ID is 255
