29
Mode 2: Common Stop, double word
Control Registers
There are only 4 control registers
control register 0 (subaddress 0)
bits 0-7
user definable module ID code. This appears in the
header data word. The default is 0.
bits 8-9
Not used, always read 0
bit 10
Selects LEADING edge recording, or BOTH edges.
1 = Both edges are recorded
0 = Leading edge ONLY is recorded (default)
bit 11
Selects readout mode.
1 = ECL PORT (FERA mode)
0 = CAMAC readout (default)
bit 12
Selects Buffer mode
1 = Multi-event buffer mode
0 = Single buffer mode. In this mode the FERA
readout is compatible with the 4300B FERA ADC.
The request delay (see register 3) must be set
appropriately. (default)
bit 13
Selects Header mode
0 = always have header (default)
1 = skip header if no data words
Mode 2 Control Registers
Control Register #0
15 14 13 12
11 10 9 8
7 6 5 4
3 2 1 0
User settable ID
code
Not used
Edge Recording
Readout Mode
Buffer Mode
Header Mode
Mode
Control Register #1
15 14 13 12
11 10 9 8
7 6 5 4
3 2 1 0
FERA Mode
Trigger out pulse
Trigger pulse
delay
Trig. clock
unit
MPI
Serial number
Control Register #2
15 14 13 12
11 10 9 8
7 6 5 4
3 2 1 0
Max. full scale time
Max. hits
Control Register #3
15 14 13 12
11 10 9 8
7 6 5 4
3 2 1 0
Not Used
Request delay