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TESTING THE MODEL 3377
The Model 3377 TDC is designed to be easily tested in situ. The com-
plete CAMAC interface, the MTD133 integrated circuits and the time
base can be checked without any cable changes.
The CAMAC data interface is readily tested by writing and reading back
arbitrary 16-bit data patterns to control register 1, via the F17•A1 and
F1•A1 commands, respectively.
The function code and subaddress lines are tested with a special
register, which exists only in the Common Start modes. On every
CAMAC instruction in the crate, the F, A, I, C and Z lines are latched at
S2. These can be read if the very next instruction is F1, A6, to a 3377
module (which is in Common Start mode).
CAMAC Bit
Read Line
A1
R1
A2
R2
A4
R3
A8
R4
F1
R5
F2
R6
F4
R7
F8
R8
F16
R9
I
R10
Z
R11
C
R12
bits R13-R15 always read 0
Control register 5 in Common Start mode controls the built in test pattern
generator. Bit 8 must be set to enable test mode (this disables the front
panel inputs). The number of pulses is selected by bits 0-4, from 0 to 31
pulses. These pulses are applied to all 32 channels. The pulse period is
selected with bits 5 and 6, as 100, 200, 400 or 800 nanoseconds. The
Common Start time out, number of hits and resolution must be set
appropriately. The test event is triggered by an F25, A0 command. This
will produce one event in the FIFO buffer, with data as selected above.
The pulse period is derived from the 40 MHz logic clock, which is used
for the control logic and the trigger system. This is independent of the
250 MHz clock used for the MTD133 time base. Since these two clocks
are independent, these test pulses can be used to approximately verify
the time base, and to approximately measure the RMS resolution of the
MTD133 time digitizers. For a discussion of the RMS error and how to
measure it correctly, please refer to the LeCroy application note,
AN-50A.
ADDITIONAL INFORMATION