Lattice Semiconductor POWR607, Руководство пользователя

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POWR607/6AT6 Evaluation Board
Figure 3. Processor Support Demo Block Diagram
Table 1 describes the DIP switch, push-button inputs, and slide potentiometer settings that control the pre-config-
ured POWR607 and emulate a variety of processor support scenarios. Use them as a reference as you follow the
procedure. To indicate a ‘1’ (logical True) on the DIP switch SW1, slide the switch towards the number indicated on
the switch body. Note the circuit board silkscreen markings for: VM3=1.8, RST=0, SEL0=0, and SEL1=0.
Table 1. Processor Support Demo Switch and Button Settings
Setting Function
DIP Switch (1, 2, 3, 4)
XX00
500ms WDT (SEL0=0, SEL1=0)
Enables a 500ms period watchdog timer (WDT).
When active, the POWR607 will monitor the terminal count (TC) value a programmable timer. Once
500ms expires, the WDT_Intr output is asserted. An amber WDT_INT LED (D11) will light momentarily
to indicate the WDT interrupt input to the processor/DSP is active. Once activated, you may reset the
WDT by pressing the push-button switch (WD_Trig) to emulate a WDT trigger event asserted by the pro-
cessor/DSP.
A red LED D5 will light when SEL0=0 and LED D6 will light when SEL1=0.
Note: For the demonstration scenario, an additional transistor circuit of the evaluation board stretches
WDT_Intr output period to make the interrupt event visible to the eye.
XX10
2 sec WDT (SEL0=1, SEL1=0)
Enables a 2-second period watchdog timer (WDT).
XX01
10 sec WDT (SEL0=0, SEL1=1)
Enables a 10-second period watchdog timer (WDT).
DC-DC#1
3.3V
(VMON1)
DC-DC#2
2.5V (-5%)
(VMON2)
DC-DC#3
1.8V
(VMON3)
1
Power,
Blue LED
R16 VM3
SW1- 8
PWR-D1
Power Supply Bus
Voltage Supervisor
Reset
(SW2)
Reset Generator
Watchdog Timer
Reset_CPU
WDT_Intr
WDT_Trig
CPU Reset or
Power Fail (IO1-D2)
WDT Interrupt (D11)
WDT Sel
POWR607
2
Reset_Pulse
WD_Trig (SW3)
Processor/DSP
SEL1, SEL0 (SW1)
00 = 500ms
01 = 2 sec
10 = 10 sec
11 = 1 min RST (SW1)
0 = No Stretch
1 = 200ms Stretch