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OpenLDI/FPD-LINK/LVDS Receiver Interface IP 

 

User Guide 
 

© 2017-2019 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at 

www.latticesemi.com/legal

.  

All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

18 

 

FPGA-IPUG-02021-1.1 

Example: 
IP configuration: Single channel FPD-Link Rx, RGB888 data type, 1039.5 Mb/s Rx Line Rate, Rx Gear 7 

Rx line rate 

(total)

  

 

 

= 

1039.5 𝑀𝑏/𝑠 ∗  4  ∗ 1

  

= 

4.158 𝐺𝑏/𝑠

 

 
Pixclk 

(Internal Pixel Clock)

   

 

= 

1039.5 𝑀𝑏/𝑠

7

  

 

= 

148.5 𝑀𝐻𝑧

 

 

Rx LVDS Input Clock   

 

= 

148.5 𝑀𝐻𝑧 ∗

7

7

    

= 

148.5 𝑀𝐻𝑧

 

 

Rx LVDS ECLK 

 

 

= 

148.5 𝑀𝐻𝑧 ∗

7

2

    

= 

519.75 𝑀𝐻𝑧

 

 

Number of Pixels per Pixel Clock 

= 

7

 7

∗ 1

    

 

= 

1 𝑃𝑖𝑥𝑒𝑙 𝑝𝑒𝑟 𝑃𝑖𝑥𝑒𝑙 𝐶𝑙𝑜𝑐𝑘

 

2.3.

 

Design and Module Description 

2.3.1.

 

FPD-Link Rx Wrapper Module 

The

 

fpd_link_rx_wrapper.v module instantiates fpd_link_rx, general purpose PLL (GPLL), test_mode, lvds71_pxlmap, 

and synchronizer modules. The fpd_link_rx module is the core module which performs the data training and serial to 
parallel conversion. GPLL

 

is used for fast clock generation. The

 

test_mode is used for internal self-checking. 

lvds71_pxlmap is used to decode the output parallel data of fpd_link_rx and convert them into pixel format. 
Synchronizers are two-level synchronizers used to sync the system reset into different clock domains before it is used 
in the system. 

fpd_link_rx_wrapper

CLKFB

RST

CLKOS

PHASEDIR

LOCK

PHASESTEP

PHASELOADREG

CLKOP

CLKI

PHASESEL

GPLL

fpd_link_rx

clk_ch0_i

d0_ch0_i

d1_ch0_i

d2_ch0_i

d3_ch0_i

clk_ch1_i

d0_ch1_i

d1_ch1_i

d2_ch1_i

d3_ch1_i

gsync_rst_i

pixel_clk_o

update_align_i

eclk_i

lock_i

bw_align_phdir_o

bw_align_phstep_o

clkwd_ch0_o

datain0/1/2/3_ch0_i

clkwd_ch1_o

bit_lock_o

word_lock_o

window_size_o

bw_align_rst_i

d0/d1/d2/d3_ch1_o

ready_align_o

ready_gddr_o

sync

lvds71_pxlmap

test_mode

d_i

rst_n_i

clk_i

d_o

datain0/1/2/3_ch1_i

test_mode_en_rx_i

pixel_clk_i

rst_n_i

comp_en

test_mode_err_o

d0/d1/d2/d3_ch0_o

sync

d_i

rst_n_i

clk_i

d_o

d0/d1/d2/d3_ch0_i

d0/d1/d2/d3_ch1_i

pixel_clk_i

de_o

vsync_o

hsync_o

pixel_d0_o

pixel_d1_o

pixel_d2_o

pixel_d3_o

rst_n_i

1'b0

clk_ch0_p_i/n_i

d1_ch0_p_i/n_i

d2_ch0_p_i/n_i

d3_ch0_p_i/n_i

d0_ch0_p_i/n_i

d1_ch1_p_i/n_i

d2_ch1_p_i/n_i

d3_ch1_p_i/n_i

d0_ch1_p_i/n_i

clk_ch1_p_i/n_i

rst_n_i

tstmode_en_i

pll_lock_o

gddr_rdy_o

bw_rdy_o

bit_lock_o

word_lock_o

pix_clk_o

pix_data0_o

pix_data1_o

pix_data2_o

pix_data3_o

hsync_o

vsync_o

de_o

tstmode_err_o

1'b0

1'b1

 

Figure 2.15. FPD-Link Rx Wrapper Block Diagram 

Содержание OpenLDI/FPD-LINK/LVDS

Страница 1: ...OpenLDI FPD LINK LVDS Receiver Interface IP User Guide FPGA IPUG 02021 1 1 April 2019 ...

Страница 2: ...2 FPD Link Rx Module 19 2 3 3 LVDS71 DDR Group Module 22 2 3 4 GDDR SYNC Module 23 2 3 5 BW ALIGN Module 24 2 3 6 CLKDIV 24 2 3 7 ECLKSYNC 24 2 3 8 GPLL 25 2 3 9 LVDS71 Pixel Map Module 25 2 3 10 Test Mode Module 26 2 3 11 Synchronizer Module 28 3 Compiler Directives and Parameter Settings 29 3 1 Parameters Settings 29 3 2 Compiler Directives 30 4 Debug Features 31 4 1 Test Mode 31 5 IP Generation...

Страница 3: ... LINK LVDS Rx Gear 7 14 Figure 2 10 Input to Output Waveform for Dual Channel OpenLDI FPD LINK LVDS Rx Gear 14 15 Figure 2 11 Output Pixel Data RGB Arrangement 15 Figure 2 12 Output Pixel Data Arrangement for Single Channel OpenLDI FPD LINK LVDS 16 Figure 2 13 Output Pixel Data Arrangement for Dual Channel OpenLDI FPD LINK LVDS 16 Figure 2 14 Clock Domain Crossing Block Diagram 17 Figure 2 15 FPD ...

Страница 4: ...ta Summary 16 Table 2 3 Clock Domain Crossing 17 Table 2 4 FPD Link Rx Pin List Summary 20 Table 2 5 FPD Link Rx Parameter List 21 Table 2 6 LVDS71 DDR Group Module Pin List 23 Table 2 7 LVDS71 DDR Group Parameter List 23 Table 2 8 LVDS71 Pixel Map Pin List Summary 26 Table 2 9 LVDS71 Pixel Map Parameter List 26 Table 2 10 Test Mode Pin List Summary 27 Table 2 11 Test Mode Parameter List 27 Table ...

Страница 5: ...nterface is a popular standard for source synchronous interfaces which consist of multiple data bits and clocks Typically 1 channel of 7 1 LVDS interface consists of five LVDS pairs 1 clock and 4 data depending on the data type it supports This document describes the use of Lattice FPGA technology for applications requiring LVDS interface and how to use the IP This design can be used in multiple c...

Страница 6: ... Protocol 7 1 LVDS Supports 3 4 LVDS data lanes per channel Supports 1 2 or 4 output pixels per pixel clock Supports interfacing up to 9 6 Gb s Table 1 2 OpenLDI FPD LINK LVDS Receiver Interface IP Features Summary IP Configuration Options Number of Channels 1 2 Data Type RGB666 RGB888 Number of Rx Lanes per Channel1 3 4 DDR Gear2 7 14 Notes 1 The Number of Rx Lanes per Channel is automatically se...

Страница 7: ...format Output interface consists of the RGB control signals pixel clock up to four pixel data per pixel clock and debug signals clk_ch0_p_i n_i d1_ch0_p_i n_i d2_ch0_p_i n_i d3_ch0_p_i n_i d0_ch0_p_i n_i d1_ch1_p_i n_i d2_ch1_p_i n_i d3_ch1_p_i n_i d0_ch1_p_i n_i clk_ch1_p_i n_i rst_n_i FPD Link Rx Wrapper Interface IP tstmode_en_i pix_clk_o pix_data0_o pix_data1_o pix_data2_o pix_data3_o hsync_o ...

Страница 8: ...t data lane 2 to LVDS 7 1 Rx Wrapper channel 0 complement of d2_ch0_p_i Not available in netlist because this is automatically set to complement by the synthesis tool d3_ch0_p_i1 I Positive LVDS Input data lane 3 to LVDS 7 1 Rx Wrapper channel 0 d3_ch0_n_i1 I Negative LVDS Input data lane 3 to LVDS 7 1 Rx Wrapper channel 0 complement of d3_ch0_p_i Not available in netlist because this is automatic...

Страница 9: ...wise this port is unused and is not available 2 LVDS channel 1 input ports are not available when single LVDS channel is selected 3 Available only when number of output pixels data is more than one See Table 2 2 for more details 4 See the Debug Features section for more details on enabling test mode 5 Can be turned on if MISC_ON is selected in the interface upon IP generation or MISC_ON is defined...

Страница 10: ...ur LVDS data pairs RGB888 or three LVDS data pairs RGB666 Maximum two LVDS 7 1 channels can be used When dual channel is selected additional data lanes are activated The clock runs at 1 7th of the data rate as per the standard for LVDS 7 1 interface The default mode for the LVDS operating system is Unbalanced as this is commonly used The maximum supported data rate per lane for LVDS is 1 2 Gb s R1...

Страница 11: ...N5 DATAIN6 DATAIN7 Previous Cycle Current Cycle RL1 n 1 RL0 n 1 GL0 n RL5 n RL4 n RL3 n RL2 n RL1 n RL0 n GL0 n 1 RL5 n 1 RL4 n 1 RL3 n 1 RL2 n 1 GL2 n 1 GL1 n 1 BL1 n BL0 n GL5 n GL4 n GL3 n GL2 n GL1 n BL1 n 1 BL0 n 1 GL5 n 1 GL4 n 1 GL3 n 1 BL3 n 1 BL2 n 1 Rsrv n CNTLF n CNTLE n BL5 n BL4 n BL3 n BL2 n Rsrv n 1 CNTLF n 1 CNTLE n 1 BL5 n 1 BL4 n 1 RL7 n 1 RL6 n 1 Rsrv n BL7 n BL6 n GL7 n GL6 n R...

Страница 12: ...B3 n 1 B2 n 1 DE n Vsync n Hsync n B5 n B4 n B3 n B2 n DE n 1 Vsync n 1 Hsync n 1 B5 n 1 B4 n 1 CLKIN DATAIN0 DATAIN1 DATAIN2 DATAIN3 DATAIN4 DATAIN5 DATAIN6 DATAIN7 Previous Cycle Current Cycle Next Cycle RL1 n 1 RL0 n 1 GL0 n RL5 n RL4 n RL3 n RL2 n RL1 n RL0 n GL0 n 1 RL5 n 1 RL4 n 1 RL3 n 1 RL2 n 1 GL2 n 1 GL1 n 1 BL1 n BL0 n GL5 n GL4 n GL3 n GL2 n GL1 n BL1 n 1 BL0 n 1 GL5 n 1 GL4 n 1 GL3 n ...

Страница 13: ...z B DATA6 n z C DATA0 n z C DATA1 n z C DATA2 n z C DATA3 n z C DATA4 n z C DATA5 n z C DATA6 n z D DATA0 n z D DATA1 n z D DATA2 n z D DATA3 n z D DATA4 n z D DATA5 n z D DATA6 n z DE_OUT VSYNC_OUT HSYNC_OUT Figure 2 7 Input to Output Waveform for Single Channel OpenLDI FPD LINK LVDS Rx Gear 7 A DATA0 n A DATA1 n A DATA2 n A DATA3 n A DATA4 n A DATA5 n A DATA6 n CLKIN DATAIN0 DATAIN1 DATAIN2 DATA...

Страница 14: ...TA6 n z B DATA0 n z B DATA1 n z B DATA2 n z B DATA3 n z B DATA4 n z B DATA5 n z B DATA6 n z C DATA0 n z C DATA1 n z C DATA2 n z C DATA3 n z C DATA4 n z C DATA5 n z C DATA6 n z D DATA0 n z D DATA1 n z D DATA2 n z D DATA3 n z D DATA4 n z D DATA5 n z D DATA6 n z E DATA0 n E DATA1 n E DATA2 n E DATA3 n E DATA4 n E DATA5 n E DATA6 n DATAIN4 DATAIN5 DATAIN6 DATAIN7 E DATA5 n 1 E DATA6 n 1 E DATA0 n 1 E ...

Страница 15: ... z C DATA3 n z C DATA4 n z C DATA5 n z C DATA6 n z D DATA0 n z D DATA1 n z D DATA2 n z D DATA3 n z D DATA4 n z D DATA5 n z D DATA6 n z E DATA0 n E DATA1 n E DATA2 n E DATA3 n E DATA4 n E DATA5 n E DATA6 n DATAIN4 DATAIN5 DATAIN6 DATAIN7 E DATA5 n 1 E DATA6 n 1 E DATA0 n 1 E DATA1 n 1 E DATA2 n 1 E DATA3 n 1 E DATA4 n 1 E DATA5 n 1 E DATA6 n 1 F DATA0 n F DATA1 n F DATA2 n F DATA3 n F DATA4 n F DAT...

Страница 16: ... in Figure 2 12 and Figure 2 13 fpd_link_rx CH 0 GEAR 7 CH1 GEAR 7 P I X 4 C H 0 P I X 3 C H 0 P I X 2 C H 0 P I X 1 C H 0 P I X 0 C H 0 pix_data0_o pix_data0_o pix_data0_o pix_data0_o pix_data1_o pix_data2_o pix_data3_o fpd_link_rx CH 0 GEAR 14 CH1 GEAR 14 P I X 4 C H 0 P I X 3 C H 0 P I X 2 C H 0 P I X 1 C H 0 P I X 0 C H 0 pix_data0_o pix_data1_o pix_data0_o pix_data1_o pix_data2_o pix_data3_o ...

Страница 17: ...d to indicate LVDS 7 1 Rx data training is done Only when bw_rdy_o is asserted valid data can be sampled and correctly transmitted by FPD Link IP The LVDS 7 1 Rx Wrapper is now ready to receive valid data Note Steps 2 and 3 are used to make sure that the system is ready to receive valid data Exact wait time cannot be specified as the design s alignment is dynamic and these flag signals are used to...

Страница 18: ... lvds71_pxlmap is used to decode the output parallel data of fpd_link_rx and convert them into pixel format Synchronizers are two level synchronizers used to sync the system reset into different clock domains before it is used in the system fpd_link_rx_wrapper CLKFB RST CLKOS PHASEDIR LOCK PHASESTEP PHASELOADREG CLKOP CLKI PHASESEL GPLL fpd_link_rx clk_ch0_i d0_ch0_i d1_ch0_i d2_ch0_i d3_ch0_i clk...

Страница 19: ...align_rst_i window_size_o 3 0 bit_lock_o word_lock_o ready_align_o clkwd_ch0 ch1_o RX_GEAR 1 0 d3_ch0 ch1_o RX_GEAR 1 0 lvds71_ddr_group pixel_clk_o d2_ch0 ch1_i d1_ch0 ch1_i d0_ch0 ch1_i d2_ch0 ch1_o RX_GEAR 1 0 d1_ch0 ch1_o RX_GEAR 1 0 d0_ch0 ch1_o RX_GEAR 1 0 pll_lock_i DELAY_LOADN DELAY_MOVE DELAY_DIRECTION DELAYF A LOADN CFLAG Z MOVE DIRECTION DELAYF A LOADN CFLAG Z MOVE DIRECTION DELAYF A LO...

Страница 20: ...data lane 2 to LVDS 7 1 RX Wrapper channel 1 d3_ch1_i 1 I LVDS LVDS Input data lane 3 to LVDS 7 1 RX Wrapper channel 1 clkwd_ch0_o RX_GEAR O LVCMOS Parallel output clkword for channel 0 d3_ ch0_o RX_GEAR O LVCMOS Parallel output data for lane 3 channel 0 d2_ ch0_o RX_GEAR O LVCMOS Parallel output data for lane 2 channel 0 d1_ ch0_o RX_GEAR O LVCMOS Parallel output data for lane 1 channel 0 d0_ ch0...

Страница 21: ... alignment is done via BW_ALIGN 0 Indicates that bit alignment is not yet done via BW_ALIGN word_lock_o 1 O LVCMOS 1 Indicates that word alignment is done via BW_ALIGN 0 Indicates that word alignment is not yet done via BW_ALIGN window_size_o 4 O LVCMOS Indicates the size of the data window in the LVDS 7 1 RX Table 2 5 FPD Link Rx Parameter List Parameters Value Description Operation NUM_RX_CH 1 2...

Страница 22: ...rt the incoming serial data into parallel format Output bus width depends on the DDR gearing set through parameter For dual channel FPD Link configuration two instances of LVDS71 DDR group are instantiated IDDR71B SCLK RST Q0 ALIGNWD Q1 Q2 Q3 Q4 Q5 Q6 ECLK D IDDR71B SCLK RST Q0 ALIGNWD Q1 Q2 Q3 Q4 Q5 Q6 ECLK D IDDR71B SCLK RST Q0 ALIGNWD Q1 Q2 Q3 Q4 Q5 Q6 ECLK D IDDR71B SCLK RST Q0 ALIGNWD Q1 Q2 Q...

Страница 23: ...DDR Must come from GDDR_SYNC alignwd_i 1 I LVCMOS Alignwd input for DDR Shifts data with respect to clock Must come from BW_ALIGN clk_phase_o RX_GEAR O LVCMOS Parallel output data clkword d3_o RX_GEAR O LVCMOS Parallel output data 3 d2_o RX_GEAR O LVCMOS Parallel output data 2 d1_o RX_GEAR O LVCMOS Parallel output data 1 d0_o RX_GEAR O LVCMOS Parallel output data 0 Table 2 7 LVDS71 DDR Group Param...

Страница 24: ... is done with respect to LVDS clock If correct training data is already sampled properly ready signal of BW_ALIGN is asserted Only then valid data can be sampled correctly by LVDS 7 1 Rx It is expected for the LVDS clock and LVDS data to be edge aligned with each other so that when alignment is done with respect to the LVDS clock LVDS data lanes are also aligned ALIGNWD SYNC_READY RX_SCLK UPDATE R...

Страница 25: ...d to generate the ECLK and start the initialization synchronization and data alignment processes CLKFB RST CLKI PHASEDIR PHASESEL PHASESTEP PHASELOADREG CLKOP CLKOS LOCK GPLL Figure 2 22 GPLL Block Diagram 2 3 9 LVDS71 Pixel Map Module lvds71_pxlmap is used to decode the output parallel data of fpd_link_rx and convert them into pixel format Up to four valid output pixel data is supported depending...

Страница 26: ... Output pixel data 1 Bus width depends on the data type selected pixel_d2_o 24 RGB88 18 RGB666 O LVCMOS Output pixel data 2 Bus width depends on the data type selected pixel_d3_o 24 RGB88 18 RGB666 O LVCMOS Output pixel data 3 Bus width depends on the data type selected de_o 1 O LVCMOS Output data enable for parallel interface hsync_o 1 O LVCMOS Output horizontal sync for parallel interface vsync_...

Страница 27: ...et to 0 when test mode is disabled datain0_ch0_i RX_GEAR I LVCMOS Input data from lane 0 of channel 0 datain1_ch0_i RX_GEAR I LVCMOS Input data from lane 1 of channel 0 datain2_ch0_i RX_GEAR I LVCMOS Input data from lane 2 of channel 0 datain3_ch0_i RX_GEAR I LVCMOS Input data from lane 3 of channel 0 datain0_ch1_i RX_GEAR I LVCMOS Input data from lane 0 of channel 1 datain1_ch1_i RX_GEAR I LVCMOS...

Страница 28: ...tem reset into different clock domains before it is used in the system SYNC d_i rst_n_i clk_i d_o Figure 2 25 Synchronizer Block Diagram Table 2 12 Synchronizer Pin List Summary Port Name Width Dir Type Description Clock s and Reset clk_i 1 I LVCMOS Input clock Input data is synchronized with this clock rst_n_i 1 I LVCMOS Asynchronous active low reset Data d_i BUS_WIDTH I LVCMOS Input data d_o BUS...

Страница 29: ...TEST_DATA value Pre defined data used when test mode is enabled For dual channel configuration the same TEST DATA is used for both channels 28 Data width for RGB888 21 Data width for RGB666 parameter TEST_DATA val Table 3 2 lists the parameters used to generate the OpenLDI FPD LINK LVDS Receiver Interface IP All parameters are either set automatically or input in the interface during the OpenLDI F...

Страница 30: ...ace IP can also be configured through compiler directives Table 3 3 OpenLDI FPD LINK LVDS Receiver Interface IP Non packaged Compiler Directives Parameters Value Description Operation NUM_RX_CH_ 1 2 Specify how many LVDS links are used 1 Single Link 2 Dual Link define NUM_RX_CH_ val RX_GEAR_ 7 14 Specify what DDR71 gearing is used 7 1 7 Gearing 14 1 14 Gearing define RX_GEAR_ val RGB 888 666 Speci...

Страница 31: ...omparison of data is enabled only after bit and word alignment is completed If data mismatch is encountered tstmode_err_o is set to high until reset is asserted or chip is powered down For dual channel configuration the same TEST_DATA is used To enable test mode 1 Configure TEST_DATA 2 Define DEBUG_ON in the defines file 3 Drive tstmode_en_i to 1 b1 4 Assert active low system reset for at least 50...

Страница 32: ...oing to the link http www latticesemi com en Support Licensing and request the free Lattice Diamond license In this form select the desired CrossLink IP for your design You may download and generate the OpenLDI FPD LINK LVDS Receiver Interface IP and fully evaluate the IP through functional simulation and implementation synthesis map place and route without an IP license The OpenLDI FPD LINK LVDS ...

Страница 33: ...be started from the Diamond design environment To start Clarity Designer 1 Create a new Diamond project for CrossLink family devices 2 From the Diamond main window choose Tools Clarity Designer or click in Diamond toolbox The Clarity Designer project dialog box is displayed 3 Select and or fill out the following items as shown in Figure 5 2 Create new Clarity design Click this to create a new Clar...

Страница 34: ...alog view The fpd link receiver dialog box is displayed as shown in Figure 5 3 Figure 5 3 Configuring OpenLDI FPD LINK LVDS Receiver Interface IP in Clarity Designer 2 Enter the Instance Name 3 Click the Customize button An IP configuration user interface is displayed as shown in Figure 5 4 From this dialog box you can select the IP configuration specific to your application 4 Input valid values i...

Страница 35: ...oduct names are trademarks or registered trademarks of their respective holders The specifications and information herein are subject to change without notice FPGA IPUG 02021 1 1 35 Figure 5 4 Configuration Tab in IP Interface 5 4 Generated IP Directory Structure and Files Figure 5 5 shows the directory structure of generated IP and supporting files Figure 5 5 OpenLDI FPD LINK LVDS Receiver Interf...

Страница 36: ...le records all the IP configuration options set through Clarity Designer It is used by IP generation script to generate configuration specific IP It is also used to reload parameter settings in the IP user interface in Clarity Designer when it is being reconfigured instance_name _inst v vhd Template for instantiating the generated soft IP top level in another user created top module Aside from the...

Страница 37: ...rs in Table 5 2 3 In Active HDL window under the Tools tab select Execute Macro 4 Select the do file project_dir fpdlinkrx_eval instance_name sim aldec run do 5 Click OK 6 Wait for the simulation to finish Table 5 2 lists the testbench directives which can be modified by setting the define in the tb_params v file Table 5 2 Testbench Compiler Directives Compiler Directive Description NUM_FRAMES Set...

Страница 38: ...on Environment The simulation environment is made up of an LVDS 7 1 model instance connected to the input of FPD Link Rx IP core instance in the testbench The LVDS 7 1 model is configured based on the FPD Link Rx IP configurations and testbench parameters The testbench can be configured as one or two Rx channels If miscellaneous signals such as pll_lock_o gddr_rdy_o bit_lock_o and word_lock_o bw_r...

Страница 39: ...IP is regenerated 5 9 Synthesizing and Implementing the IP In Clarity Designer the Clarity Designer project file sbx is added to Lattice Diamond as a source file after all IPs are generated Note that default Diamond strategy sty and default Diamond preference file lpf are used When using the sbx approach import the recommended strategy from project_dir fpdlinkrx_eval instance_name impl lifmd lse o...

Страница 40: ...1 Enabling Hardware Evaluation in Diamond Choose Project Active Strategy Translate Design Settings The hardware evaluation capability may be enabled or disabled in the Strategy dialog box It is enabled by default 5 11 Updating Regenerating the IP The Clarity Designer user interface allows you to update the local IPs from the Lattice IP server The updated IP can be used to regenerate the IP in the ...

Страница 41: ...ks or registered trademarks of their respective holders The specifications and information herein are subject to change without notice FPGA IPUG 02021 1 1 41 References For more information about CrossLink devices refer to the CrossLink Family Data Sheet FPGA DS 02007 Software documentation Clarity Designer 3 8 User Manual Diamond 3 9 1 User Guide Technical Support Assistance Submit a technical su...

Страница 42: ...about the usage of Clarity Designer refer to the Clarity Designer and Diamond help system For more information on the Diamond design tools visit the Lattice web site at www latticesemi com Products DesignSoftwareAndIP Table A 1 Resource Utilization1 IP User Configurable Parameters Slices LUTs Registers sysMEM EBRs Target fMAX MHz 2 1x7 Rx RGB888 154 233 119 0 150 2x7 Rx RGB888 168 237 143 0 150 1x...

Страница 43: ...s are trademarks or registered trademarks of their respective holders The specifications and information herein are subject to change without notice FPGA IPUG 02021 1 1 43 Appendix B What is Not Supported The IP does not support configuration through registers The IP has the following limitations Odd multiple number of pixels is not supported when Rx Gear 14 is used For Dual Channel configuration ...

Страница 44: ...formation herein are subject to change without notice 44 FPGA IPUG 02021 1 1 Revision History Revision 1 1 IP Version 1 0 April 2019 Section Change Summary Introduction Specified that this user guide can be used for IP design versions 1 x IP Generation and Evaluation In Licensing the IP modified the instructions for requesting free license Revision History Updated revision history table to new tem...

Страница 45: ...www latticesemi com ...

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