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MIPI DSI to OpenLDI/FPD-Link/LVDS Interface Bridge Soft IP

User Guide

© 2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at

www.latticesemi.com/legal

. All other brand or product names are

trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

8

FPGA-IPUG-02003-1.2

shows the MIPI DSI to OpenLDI/FPD-Link/LVDS Interface Bridge IP (1:2, Split) block diagram.

DPHY Common Interface

Wrapper

Hard

DPHY

RX Global

Operations

Controller

LP HS

Controller

Capture

Controller

Byte2Pixel

FIFO

PLL

clk_byte_fr from DPHY

clk_pixel_i

clk_byte_fr

from PLL

vsync_o

hsync_o

de_o

Pixel data

clk_ref_i

or

clk_byte_fr from

DPHY

Lane Distr

p_odd_o

LVDS

Wrapper

clk_ch0_p_o
clk_ch0_n_o
d0_ch0_p_o
d0_ch0_n_o
d1_ch0_p_o
d1_ch0_n_o
d2_ch0_p_o
d2_ch0_n_o
d3_ch0_p_o
d3_ch0_n_o

OSC

clk_lp_ctrl

eclk

clk_ch0_p_i
clk_ch0_n_i

d0_ch0_p_i
d0_ch0_n_i

d1_ch0_p_i
d1_ch0_n_i

d2_ch0_p_i
d2_ch0_n_i

d3_ch0_p_i
d3_ch0_n_i

clk_ref_i

or

clk_byte_fr from

DPHY

clk_ref_i

or

clk_byte_fr from

DPHY

clk_ch1_p_o
clk_ch1_n_o
d0_ch1_p_o
d0_ch1_n_o
d1_ch1_p_o
d1_ch1_n_o
d2_ch1_p_o
d2_ch1_n_o
d3_ch1_p_o
d3_ch1_n_o

Figure 2.3. MIPI DSI to OpenLDI/FPD-Link/LVDS Interface Bridge IP (1:2, Split) Block Diagram

shows the MIPI DSI to OpenLDI/FPD-Link/LVDS Interface Bridge IP (2:2) block diagram.

DPHY Common Interface

Wrapper

Hard

DPHY

RX Global

Operations

Controller

LP HS

Controller

Capture

Controller

Byte2Pixel

FIFO

PLL

clk_ch0_p_i
clk_ch0_n_i

clk_byte_fr from DPHY

clk_pixel_i

(channel 0)

vsync_o

hsync_o

de_o

Pixel data

clk_ref_i

or

clk_byte_fr from

DPHY channel 0

d0_ch0_p_i
d0_ch0_n_i

d1_ch0_p_i
d1_ch0_n_i

d2_ch0_p_i
d2_ch0_n_i

d3_ch0_p_i
d3_ch0_n_i

Lane Distr

p_odd_o

LVDS

Wrapper

clk_ch0_p_o
clk_ch0_n_o

d0_ch0_p_o
d0_ch0_n_o

d1_ch0_p_o
d1_ch0_n_o

d2_ch0_p_o
d2_ch0_n_o

d3_ch0_p_o
d3_ch0_n_o

OSC

clk_lp_ctrl

eclk

DPHY Common Interface

Wrapper

Hard

DPHY

Capture

Controller

Byte2Pixel

FIFO

clk_ch1_p_i
clk_ch1_n_i

vsync_o

hsync_o

de_o

Pixel data

d0_ch1_p_i
d0_ch1_n_i

d1_ch1_p_i
d1_ch1_n_i

d2_ch1_p_i
d2_ch1_n_i

d3_ch1_p_i
d3_ch1_n_i

Lane Distr

p_odd_o

LVDS

Wrapper

clk_ch1_p_o
clk_ch1_n_o

d0_ch1_p_o
d0_ch1_n_o

d1_ch1_p_o
d1_ch1_n_o

d2_ch1_p_o
d2_ch1_n_o

d3_ch1_p_o
d3_ch1_n_o

clk_byte_fr

clk_byte_fr

clk_pixel_i

(channel 1)

clk_ref_i

or

clk_byte_fr from

DPHY channel 0

clk_ref_i

or

clk_byte_fr from

DPHY channel 0

Figure 2.4. MIPI DSI to OpenLDI/FPD-Link/LVDS Interface Bridge IP (2:2) Block Diagram

The MIPI DSI receive interface has one MIPI D-PHY clock lane and four MIPI D-PHY data lanes. The clock lane is center-
aligned to the data lanes. The clock lane can either be continuous (high speed only, HS_ONLY) or non-continuous
(HS_LP).

When the clock lane is non-continuous, proper transition from low power (LP) to high speed (HS) mode of clock lane is
required. The data lanes also require proper transition from LP to HS modes. In HS mode, data stream from each data

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Содержание MIPI

Страница 1: ...MIPI DSI to OpenLDI FPD Link LVDS Interface Bridge Soft IP User Guide FPGA IPUG 02003 Version 1 2 November 2016 ...

Страница 2: ...ace Wrapper 10 2 3 Rx Global Operations Controller 10 2 4 Capture Controller 11 2 5 Byte2Pixel 12 2 6 Lane Distribution 12 2 7 LVDS Wrapper 12 2 8 Reset and Clocking 13 3 Parameter Settings 15 4 IP Generation and Evaluation 16 4 1 Licensing the IP 16 4 2 Getting Started 16 4 3 Generating IP in Clarity Designer 17 4 4 Generated IP Directory Structure and Files 20 4 5 Running Functional Simulation 2...

Страница 3: ... Link Split Timing Diagram 10 Figure 2 9 MIPI D PHY Clock Lane Module State Diagram 11 Figure 2 10 MIPI D PHY Data Lane Module State Diagram 11 Figure 4 1 Clarity Designer Window 16 Figure 4 2 Starting Clarity Designer from Diamond Design Environment 17 Figure 4 3 Configuring MIPI DSI to OpenLDI FPD Link LVDS Interface Bridge IP in Clarity Designer 18 Figure 4 4 Configuration Tab in IP GUI 18 Figu...

Страница 4: ... vendors can provide very fast interfacing capabilities For a cost effective solution displays can be replaced with newer display and the processor can be retained Low Voltage Differential Signaling LVDS interface has become popular to support fast data rates of video transmission for Flat Panel Display Link FPD Link connections Application Processor DCK MIPI DSI LVDS DCK0 D 0 3 D0 D3 DCK1 D 4 7 F...

Страница 5: ...re The nomenclature used in this document is based on Verilog HDL This includes radix indications and logical operators 1 3 2 Data Ordering and Data Types The highest bit within a data bus is the most significant bit Single bit data stream from each MIPI DSI data lane is deserialized into 8 bit or 16 bit parallel data where bit 0 is the first received bit The size of parallel data depends on the R...

Страница 6: ..._ch0_p_o clk_ch0_n_o d0_ch0_p_o d0_ch0_n_o d1_ch0_p_o d1_ch0_n_o d2_ch0_p_o d2_ch0_n_o d3_ch0_p_o d3_ch0_n_o clk_ch1_p_o clk_ch1_n_o d0_ch1_p_o d0_ch1_n_o d1_ch1_p_o d1_ch1_n_o d2_ch1_p_o d2_ch1_n_o d3_ch1_p_o d3_ch1_n_o lock_pll_o pll_lol_o ready_o Figure 2 1 MIPI DSI to OpenLDI FPD Link LVDS Interface Bridge IP Block Diagram Table 2 1 MIPI DSI to OpenLDI FPD Link LVDS Interface Bridge IP Pin Fun...

Страница 7: ...vailable only for configurations with two Tx channels d1_ch1_p_o d1_ch1_n_o IO LVDS channel 1 data lane 1 Available only for configurations with two Tx channels d2_ ch1_p_o d2_ ch1_n_o IO LVDS channel 1 data lane 2 Available only for configurations with two Tx channels d3_ ch1_p_o d3_ ch1_n_o IO LVDS channel 1 data lane 3 Available only for configurations with two Tx channels and RGB888 data type ...

Страница 8: ... IP 2 2 block diagram DPHY Common Interface Wrapper Hard DPHY RX Global Operations Controller LP HS Controller Capture Controller Byte2Pixel FIFO PLL clk_ch0_p_i clk_ch0_n_i clk_byte_fr from DPHY clk_pixel_i channel 0 vsync_o hsync_o de_o Pixel data clk_ref_i or clk_byte_fr from DPHY channel 0 d0_ch0_p_i d0_ch0_n_i d1_ch0_p_i d1_ch0_n_i d2_ch0_p_i d2_ch0_n_i d3_ch0_p_i d3_ch0_n_i Lane Distr p_odd_...

Страница 9: ...RGB data and control signals extracted from DSI packets are transmitted over FPD Link interface such that output is compliant to OpenLDI unbalanced format as shown in Figure 2 6 Figure 2 8 Control signals include data enable DE vertical and horizontal sync flags VSYNC and HSYNC Reserved bits RES are tied to 0 VSYNC HSYNC DE VSYNC HSYNC DE R0 G1 B2 R1 G2 B3 R2 G3 B4 R3 G4 B5 R4 G5 R5 B0 G0 B1 R0 G1...

Страница 10: ...ncoming packets are split into the two channels in an alternate manner The first pixel received is transmitted over LVDS channel 0 while the next pixel received is transmitted over LVDS channel 1 at the same clock cycle as shown in Figure 2 8 The same approach is implemented regardless of TX_GEAR setting The dual MIPI DSI to dual FPD Link configuration is two instances of single MIPI DSI to single...

Страница 11: ... Controller When two Rx channels are enabled each channel has its own capture controller This block takes data bytes from D PHY Common Interface Wrapper and detects short and long packets defined by MIPI DSI to generate sync signals and extract video data and other control parameters Table 2 2 shows outputs of this block that are relevant to MIPI DSI to OpenLDI FPD Link LVDS Interface Bridge IP Ta...

Страница 12: ...red to pixel clock domain using synchronization registers Since only DSI Non Burst Mode with Sync Pulses is supported the generation of VSYNC and HSYNC control signals is dependent on the MIPI DSI host device as follows VSYNC goes active high and inactive low when the VSYNC Start and VSYNC End short packets are seen respectively HSYNC goes active high when the HSYNC Start VSYNC Start and VSYNC End...

Страница 13: ...able of clock lane is tied to VCC Continuous byte clock is generated by hard D PHY IP and used as PLL reference clock Internal PLL generates eclk used to serialize data A clock divider is used to generate pixel clock inside the lvds wrapper When MIPI D PHY clock is non continuous an external clock source clk_ref_i is needed for PLL reference clock Internal PLL generates continuous byte clock and e...

Страница 14: ...change without notice 14 FPGA IPUG 02003 1 2 Table 2 4 Supported Data Rates for MIPI DSI to OpenLDI FPD Link LVDS Interface Bridge IP Configurations Configuration D PHY line rate Mb s DCK MHz Data Type RX_GEAR TX_GEAR Single DSI to Single FPD Link RGB666 8 7 160 675 40 337 5 14 675 771 42 337 5 385 74 RGB888 RGB666_LOOSE 8 7 160 900 40 450 16 14 900 1028 57 450 514 28 Single DSI to Dual FPD Link R...

Страница 15: ...VDS Transmit interface FPD Link Number of Tx lanes Read only 3 or 4 Derived from data type 3 lanes for RGB666 while 4 lanes for RGB888 Tx gearing Read only 7 or 14 Gearbox ratio of transmit interface automatically selected based on Rx data rate see Reset and Clocking section on page 13 Rx Line Rate User input See Table 2 4 Data rate per MIPI D PHY lane Tx Line Rate Read only See Table 2 3 Data rat...

Страница 16: ...ng Lattice Diamond license or providing your MacID along with the IP details You may download or generate the MIPI DSI to OpenLDI FPD Link LVDS Interface Bridge IP and fully evaluate it through functional simulation and implementation synthesis map place and route without the IP license The MIPI DSI to OpenLDI FPD Link LVDS Interface Bridge IP also supports Lattice s IP hardware evaluation capabil...

Страница 17: ...y Designer or click in Diamond toolbox The Clarity Designer project dialog box is displayed 3 Select and fill out the following items as shown in Figure 4 2 Create new Clarity design Choose to create a new Clarity Design project directory in which the MIPI DSI to OpenLDI FPD Link LVDS Interface Bridge IP will be generated Design Location Clarity Design project directory path Design Name Clarity De...

Страница 18: ...ecifications and information herein are subject to change without notice 18 FPGA IPUG 02003 1 2 Figure 4 3 Configuring MIPI DSI to OpenLDI FPD Link LVDS Interface Bridge IP in Clarity Designer 2 Enter the Instance Name 3 Click the Customize button An IP configuration interface is displayed as shown in Figure 4 4 and Figure 4 5 From this dialog box you can select the IP parameter options specific t...

Страница 19: ...ed trademarks of their respective holders The specifications and information herein are subject to change without notice FPGA IPUG 02003 1 2 19 Figure 4 5 Video Tab in IP GUI 4 Select the required parameters and click the Configure button 5 Click Close 6 Click in the toolbox Clarity Designer generates all the IPs and modules and creates a top module to wrap them For detailed instructions on how to...

Страница 20: ...log parameters file which contains required compiler directives to successfully configure IP during synthesis and simulation instance_name lpc Lattice Parameters Configuration file This file records all the IP configuration options set through Clarity Designer It is used by IP generation script to generate configuration specific IP It is also used to reload parameter settings in the IP GUI in Clar...

Страница 21: ...ted for example set design_path C my_designs DesignA e Specify design instance name same as the instance name specified in Clarity Designer for example set design_inst DesignA_inst f Specify Lattice Diamond primitive path to where it is installed for example set diamond_dir C lscc diamond 3 8_x64 4 Update testbench parameters and or directives to customize data size clock and or other settings See...

Страница 22: ...e duration in ps for Horizontal Back Porch low power state used for LP blanking in Non burst sync events and Burst mode DSI_LPS_HFP_DURATION Used to set the duration in ps for Horizontal Front Porch low power state used for LP blanking in Non burst sync events and Burst mode NON_BURST_SYNC_EVENTS Used to set the video mode type to Non burst sync events Not supported by DUT BURST_MODE Used to set t...

Страница 23: ...ed model is connected to the MIPI DSI to OpenLDI FPD Link LVDS Interface Bridge IP instance DUT in the testbench The DSI model is configured based on the DUT configurations and testbench configurations The testbench monitors assertion of the ready_o before sending the video data to the DUT if miscellaneous signals are enabled The testbench also transmits reference clock to the DUT if D PHY clock m...

Страница 24: ...o not need to be instantiated one by one manually The top level file and the other Verilog source files are provided in project_dir These files are refreshed each time the IP is regenerated A Verilog instance template instance_name _inst v or VHDL instance template instance_name _inst vhd is also provided as a guide if the design is to be included in another top level module 4 9 Synthesizing and I...

Страница 25: ...oose File Open Project 2 In the Open Project dialog box browse to project_dir dsi2fpdlink_eval instance_name impl lifmd synthesis_tool 3 Select and open instance_name _top ldf At this point all of the files needed to support top level synthesis and implementation are imported to the project 4 Select the Process tab in the left hand GUI window 5 Implement the complete design via the standard Diamon...

Страница 26: ...r allows you to update the local IPs from the Lattice IP server The updated IP can be used to regenerate the IP instance in the design To change the parameters of the IP used in the design the IP must also be regenerated 4 11 1 Regenerating an IP in Clarity Designer To regenerate IP in Clarity Designer 1 In the Builder tab right click the IP instance to be regenerated and select Config in the menu...

Страница 27: ...e without notice FPGA IPUG 02003 1 2 27 References For more information about CrossLink devices refer to FPGA DS 02007 CrossLink Family Data Sheet For further information on interface standards refer to MIPI Alliance Specification for D PHY version 1 1 November 7 2011 www mipi org MIPI Alliance Specification for Display Serial Interface version 1 1 November 22 2011 www mipi org Open LVDS Display I...

Страница 28: ... I Os do not count miscellaneous status signals The values of fMAX shown are based on continuous byte clock The Target fMAX column shows target byte clock frequency for each configuration See the Reset and Clocking section on page 13 for more details on supported clock frequencies Table A 1 Resource Utilization IP User Configurable Parameters Slices LUTs Registers sysMEM EBRs Programmable IOs Actu...

Страница 29: ...on correction of packet header in a short and a long packet Checksum calculation and error detection in long packet Command mode operation in MIPI DSI Non burst mode with sync events and burst mode in MIPI DSI DCS parsing in MIPI DSI Interlaced video scan mode The MIPI DSI to OpenLDI FPD Link LVDS Interface Bridge IP has the following design limitations Maximum value of word count in a long packet...

Страница 30: ...g free license July 2016 1 1 Updated document number the previous document number was IPUG122 Updated Synplify Pro version in Table 1 1 MIPI DSI to OpenLDI FPD Link LVDS Interface Bridge IP Quick Facts and added simulation Updated Figure 2 3 MIPI DSI to OpenLDI FPD Link LVDS Interface Bridge IP 1 2 Split Block Diagram Updated description of D PHY Clock Frequency in Table 3 1 MIPI DSI to OpenLDI FP...

Страница 31: ...7th Floor 111 SW 5th Avenue Portland OR 97204 USA T 503 268 8000 www latticesemi com ...

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