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MIPI DSI to OpenLDI/FPD-Link/LVDS Interface Bridge Soft IP
User Guide
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FPGA-IPUG-02003-1.2 11
Figure 2.9. MIPI D-PHY Clock Lane Module State Diagram
Similarly, HS termination enable of data lanes becomes high after proper LP to HS transition is detected on data lane 0.
A free-running byte clock is used for this function. The required LP to HS transition on data lanes is shown in
Figure 2.10
as per MIPI D-PHY Specification version 1.1.
Figure 2.10. MIPI D-PHY Data Lane Module State Diagram
2.4. Capture Controller
When two Rx channels are enabled, each channel has its own capture controller. This block takes data bytes from
D-PHY Common Interface Wrapper and detects short and long packets defined by MIPI DSI to generate sync signals and
extract video data and other control parameters.
Table 2.2 shows outputs of this block that are relevant to MIPI DSI to
OpenLDI/FPD-Link/LVDS Interface Bridge IP.
Table 2.2. Capture Controller Outputs
Port Name Direction Function Description
payload_en_o Output Payload data enable to indicate when byte to pixel conversion is required (active high)
payload_o[MSB:0] Output Video data or payload. Data width is Rx lanes * RX_GEAR
sp_en_o
Output
Short packet enable. Goes high for 1 byte clock cycle when short packet is detected (active
high)
sp2_en_o
Output
Short packet enable. Goes high for 1 byte clock cycle when short packet is detected from
the higher byte when RX_GEAR=16 (active high)
lp_en_o
Output
Long packet enable. Goes high for 1 byte clock cycle when long packet is detected (active
high)