5
MachXO Standard Evaluation Board
Lattice Semiconductor
Revisions 001 & 002 User’s Guide
Adjacent to JP25-27 are current sense resistors. These permit the measurement of the current flowing from each
of the power supplies. A single resistor can be moved to permit 1.2V, 3.3V, or V
ADJ
to supply V
CORE
to the MachXO.
Table 2. MachXO Core Voltage Selection
The remaining current sense resistors permit the measurement of the V
CCIO
current draw.
Table 3. MachXO I/O Voltage Rails
Four V
CCIO
banks are available on the MachXO Standard Evaluation board. Three of the four I/O banks can be
selected. V
CCIO2
is always powered at 3.3V. This forces the JTAG interface to run at 3.3V. V
CCIO0
, V
CCIO1
, and
V
CCIO3
can be altered using jumpers.
Table 4. MachXO I/O Voltage Selection
Figure 2. MachXO Standard Evaluation Board
Programmability
The programming interface for the MachXO (and ispClock5610) is located in the northwest corner of the board.
The 1x10 header, JP7, is the connection point for the JTAG download cable. Jumpers JP6 and JP8 determine how
the TDI/TDO chain and TMS pins behave.
Important Note:
The board must be un-powered when connecting, disconnecting, or reconnecting the ispDOWN-
LOAD Cable. Always connect the ispDOWNLOAD Cable's GND pin (black wire), before connecting any other JTAG
pins. Failure to follow these procedures can in result in damage to the MachXO device and render the board inop-
erable.
Resistor
Voltage Supplied
to the MachXO Core
R141
V
ADJ
R142
1.2V
R144
3.3V
Resistor
I/O Bank Voltage
R143
1.2V
R145
3.3V
R148
V
ADJ
Jumper Block
V
CCIO
Controlled
JP20
1-2: V
CCIO1
= 3.3V
3-4: V
CCIO1
= V
ADJ
5-6: V
CCIO1
= 1.2V
JP21
1-2: V
CCIO0
= 3.3V
3-4: V
CCIO0
= V
ADJ
5-6: V
CCIO0
= 1.2V
JP22
1-2: V
CCIO3
= 3.3V
3-4: V
CCIO3
= V
ADJ
5-6: V
CCIO3
= 1.2V
Pin 1
Pin 6
