Lattice Semiconductor MachXO, Руководство пользователя

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MachXO Standard Evaluation Board
Lattice Semiconductor Revisions 001 & 002 User’s Guide
See the ispClock5610 Family Data Sheet and the Lattice PAC-Designer
®
design software for information about pro-
gramming the ispClock. More information and software downloads can be found on the Lattice web site at www.lat-
ticesemi.com/ispclock.
ispClock Configuration
The ispClock5610 has multiple configuration pins. The evaluation board includes a number of headers on the board
allowing these configuration pins to be asserted, deasserted, or controlled from the MachXO. The headers have a
general format as shown in Figure 7.
Figure 7. ispClock Configuration Headers
JP11 - JP17 configure all of the ispClock features. Table 11 shows which jumper block controls which ispClock pin.
Refer to the ispClock5610 Family Data Sheet to understand what function each pin performs.
Table 11. ispClock5610 Clock Source
The ispClock has the ability to be programmed with four separate profiles. The profiles are selected using the
PS1:0 input pins. The ispClock is programmed with a unique personality in profile 0. None of the remaining profiles
provide additional frequencies.
Profile 0 is configured to use the ispClock PLL to generate several output frequencies from the base 33MHz input
frequency. The outputs are:
• Output 0: 4x input
• Output 1: 2x input
• Output 2: 1x input
• Output 3: 0.5x input
• Output 4: 0.25x input
Some applications may not require the ispClock to use the PLL to generate higher frequency clocks. It is possible
to turn the ispClock into a clock buffer chip. This is done by moving the PLL Bypass jumper from the default loca-
tion. The PLL will no longer be included in the clock frequency generation. If Profile 0 is still selected the post PLL
clock dividers will still be active, causing the output frequencies to drop dramatically. If a 1:1 input to output fre-
quency ratio is desired the PS1:0 jumpers can be used to select any profile other than Profile 0.
Jumper Block IspClock Control Factory Default Setting
JP11 PS0 5-6
JP12 PLL Bypass 5-6
JP13 OEx 5-6
JP14 GOE 5-6
JP15 SGATE 1-2
JP16 PS1 5-6
JP17 OEy 5-6
Pin 1
P u ll-do w n P u ll- u p
MachXO