Lattice Semiconductor HDMI-VIP-IB-EVN, Руководство пользователя

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HDMI VIP Input Bridge Board
Evaluation Board User Guide
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trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-EB-02008-1.0 7
High-Speed Headers
There are two 60 pin high speed headers, connectors J1 and J2, used to connect to a host board.
Table 3.1 Connector J1
J1 Connector Pin Signal Name SiI1127A Pin J1 Connector Pin Signal Name SiI1127A Pin
1 3.3 V — 31 UP_GPIO26 Q25
2 3.3 V — 32 UP_GPIO19 Q18
3 3.3 V — 33 GND —
4 3.3 V — 34 UP_GPIO20 Q19
5 UP_GPIO31 Q30 35 GND —
6 UP_GPIO5 Q4 36 GND —
7 UP_GPIO32 Q31 37 UP_GPIO27 Q26
8 UP_GPIO6 Q5 38 GND —
9 UP_GPIO33 Q32 39 UP_GPIO28 Q27
10 UP_GPIO7 Q6 40 GND —
11 UP_GPIO34 Q33 41 RX_SDO SDO
12 UP_GPIO8 Q7 42 UP_GPIO21 —
13 UP_GPIO1 Q0 43 RX_WS WS
14 UP_GPIO9 Q8 44 UP_GPIO22 Q21
15 UP_GPIO2 Q1 45 RX_SCK SCK
16 UP_GPIO10 Q9 46 UP_GPIO23 Q22
17 GND — 47 RX_MCLK MCLK
18 GND — 48 UP_GPIO24 Q23
19 GND — 49 CEC_D CEC_D
20 GND — 50 UP_GPIO29 Q28
21 UP_GPIO13 Q12 51 RX_SCDT GPIO1/SCDT
22 GND — 52 UP_GPIO30 Q29
23 UP_GPIO11 Q10 53 GND —
24 UP_GPIO14 Q13 54 GND —
25 UP_GPIO35 Q34 55 GND —
26 UP_GPIO12 Q11 56 GND —
27 UP_GPIO36 Q35 57 2.5 V —
28 UP_GPIO17 Q16 58 2.5 V —
29 UP_GPIO25 Q24 59 2.5 V —
30 UP_GPIO18 Q17 60 2.5 V —