HDMI VIP Input Bridge Board
Evaluation Board User Guide
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. All other brand or product names are
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6
FPGA-EB-02008-1.0
Functional Description
The SiI1127A device receives up to 1080p @ 60 Hz HDMI-compliant digital audio and video from either HDMI Type A
Connector Port 1 or Port 2 and transmits RGB or YCbCr parallel video and I
2
S or SPDIF audio to connectors J1 and J2.
The SiI1127A device does not support HDCP decryption, therefore can only receive unencrypted video.
Sil1127
Parallel Video
I2S
I2C
SPDIF
C
o
n
n
e
cto
rs
J1
/J
2
HDMI/DVI Input
HDMI/DVI Input
HDMI
Type A
HDMI
Type A
Figure 2.1 Functional Block Diagram
The SiI1127A device is configured using the I
2
C interface from connector J2. The I
2
C registers monitor and control all
functions of the SiI1127A device, including selection of input. The Device Address Select Pin CI2CA on the SiI1127A
device is pulled low. Refer to
Table 2.1
for the corresponding I
2
C Address. For configuration, refer to the
SiI9223/9233/9127 HDMI Receivers Programmer’s Reference (SiI-PR-1019) for detailed information.
The Programmer’s
Reference requires an NDA with Lattice Semiconductor.
Table 2.1 SiI1127A 7-bit I
2
C Address
Block
CI2CA = 0
Device Address
0x30
2.1.
Switches
There is one push button switch, SW1, which controls the reset signal RX_RST. When pressing the push-button, logic 0
will be sent to the SiI1127A RESET# pin. RX_RST is connected to GSRN on connecter J1, allowing SW1 to control the
reset signal for other connected boards.
There is one slide switch, SW2, which in connected to GPIO3/MUTEOUT of the SiI1127A device and Pin 28 of connector
J2. When this connection is being driven by either SiI1127A device or connector J2, SW2 should be placed in the HIGH
position (4.7K Ω pull-up resistor to 3.3 V) to prevent any contention.
2.2.
HDMI Interface
There are two HDMI Type A connectors for connecting the HDMI VIP Input Board to an HDMI Source. ESD protection is
provided on the TMDS signals.
