3
ECP5 PCI Express Board User’s Guide
Caution: The ECP5 PCI Express Board contains ESD-sensitive components. ESD safe practices should be fol-
lowed while handling and using the evaluation board.
ECP5 Device
This board features an ECP5 FPGA in a 756-ball caBGA with a 1.1 V core supply. A complete description of this
device can be found in DS1044,
ECP5 Family Data Sheet
.
Note: The connections referenced in this document refer to the LFE5UM-85F-7MG756BC d
evice.
Applying Power to the Board
The ECP5 PCI Express Board is ready to power on. The board can be supplied with power from a PCI Express
host system or standalone with an external wall power module.
The 12 V DC input power source is fused with a surface mounted fuse, as noted in Table 1.
Table 1. Board Power Supply Fuses
(See Appendix B, "Power Supplies" sheet)
The board may be plugged into a host PC. Only plug the board into a PCI Express slot when the system is powered
off. Once inserted, the PC can be safely powered on.
Using the evaluation board outside of a PC chassis supply requires the factory-supplied wall supply module. Use of
other supplies is not suggested.
Figure 2. Power Distribution Scheme
(See Appendix B, "Power Supplies" sheet)
Programming/FPGA Configuration
The ECP5 PCI Express Board has a built-in download controller for programming the ECP5 FPGA. The built-in
module consists of a USB Type-B connector and a USB UART device. To use the built-in down- load cable, simply
connect a standard USB cable (a USB-B to USB-A cable is included with the ECP5 PCI Express Board) from J5 to
Fuse Designator
Description
F1
12 V Input Supply Fuse
Power Supply Block Diagram
12_0V
(5A Fused)
2_5V, +2.5 V, 1.1 A
3_3V, +3.3 V, 1.35 A
SERDES 1_2V, +1.2 V, 500 mA
LPDDR3, VDD1 1_2V, +1.2 V, 500 mA
SERDES 1_1V, +1.1 V, 500 mA
LPDDR3, VDD1 1_8V, +1.8 V, 100 mA
1_5V, +1.5 V, 1.1 A
VCC_CORE, +1.1 V, 1.35 A
SW
SW
LDO
LDO
LDO
SW
SW
