Lapis ML610Q111, Руководство пользователя

Страница: 91 / 402

ML610Q111/ML610Q112 User’s Manual
Chapter 6 Clock Generation Circuit
FEUL610Q111 6-10
6.3.3 Switching of System Clock
The system clock can be switched between high-speed clock (HSCLK) and low-speed clock (LSCLK) by using the
frequency control registers (FCON0, FCON1).
Figure 6-7 shows a flow of system clock switching processing (HSCLK
→
LSCLK) and Figure 6-8 shows a flow of system
clock switching processing (LSCLK
→
HSCLK).
Figure 6-7 Flow of System Clock Switching Processing (HSCLK
→
LSCLK)
Figure 6-8 Flow of System Clock Switching Processing (LSCLK
→
HSCLK)
Note :
If the system clock is switched from a low-speed clock to a high-speed clock before the high-speed clock (HSCLK) starts
oscillation, the CPU becomes inactive until HSCLK starts clock supply to the peripheral circuits.
System clock switching
ENOSC
←
”1”
Wait until oscillation
stabilizes (T
WAIT
)
SYSCLK
←
”1”
High-speed operation mode
T
WAIT
= 3ms @bult-in PLL oscillation mode
T
WAIT
= 1ms @External clock input mode
Start of high-speed oscillation
System clock switching (Low-speed clock
→
High-speed clock)
A high-speed
clock is used?
It is continuous use about a low-speed clock (LSCLK).
No
Yes
System clock switching (High-speed clock
→
Low-speed clock)
System clock switching
Low-speed operation mode
Stop of high-speed oscillation
(* do not need to stop the oscillation if the high-speed clock is used
for any peripheral)
SYSCLK
←
”0”
ENOSC
←
”0”