Lanner NCA-5310, Руководство пользователя

Страница: 89 / 91

NCA-5310 User Manual
89
SMU Common Options

APBDIS
1
Turns Algorithm Performance Boost as ON to fixed
SOC Pstate.
This setting governs the boost behavior of the core. For high-
performance computing workloads, we recommend lock maximum
boost state (memory p-states is necessary for Rome. P0 the highest
performance memory p-state)
Fixed SOC
Pstate
Advanced

NBIO
Common Options

SMU Common Options

Fixed SOC Pstate
P0
Need to set APBDIS=1 and recommend fixed SOC
Pstate at P0
Preferred IO
Advanced

NBIO
Common Options

Preferred IO
Manual
Enable/Disable Preferred-IO function.
Auto
Note: This setting will provide enhanced priority to a single PCI
device and increase the PCI clock. For systems with a single
Mellanox PCI card, this needs to be enabled when using a high-
performance, low-latency interconnect.
Preferred IO
Bus
Advanced

NBIO
Common Options

Preferred IO Bus
C0
1. Check which one you use, PCI device or PCI slot .
2. Use command lspci in CLI to determine which PCI
device the Mellanox card is hosted on, and set it as
this address.
cTDP Control
Advanced

NBIO
Common Options

cTDP Control
Manual Set configurable Thermal Design Point by manually
Auto Use default configurable Thermal Design Point
Note: Each CPU has a minimum and maximum cTDP threshold.
Ensure cTDP=PPL in BIOS.
PPL
Advanced

NBIO
Common Options

PPL
Manual Set Package Power Limit by manually
Auto Use default Package Power Limit
Note: Every CPU has a maximum PPL limit. Ensure PPL=cTDP. PPL
can be set lower than the cTDP minimum
IOMMU
Advanced

NBIO
Common Options

NB
configuration

IOMMU
Disabled
Disable/enable IOMMU function (Note: Special case for
2x64 cores with SMT=ON. You should set IOMMU=ON,
Local APIC Mode=Auto and add iommu=pt kernel boot
parameter.)
Enable
NUMA nodes
per socket
Advanced

DF
Common Options

Memory Addressing

NUMA nodes per
socket
NPS0
Interleave memory accesses across all channels in both
sockets. (not recommended)
NPS1
Interleave memory accesses across all eight channels
(ABCDEFGH) in each socket report 1 NUMA node per
socket
NPS2
Interleave memory accesses across groups of 4 channels
(ABCD/EFGH) in each socket report 2 NUMA nodes per
socket