5
X
RS-232,485 + 2
X
E
THERNET
/2 M
BIT
/
S
G.703 (G.704) M
ULTIPLEXER
O
PERATING
M
ANUAL
IOA81-1E
12
August 2004
3.3 Structure of 2048 kbit/s signal frame
The frame of 2048 kbit/s signal, compliant with the ITU-T G.704 Recommendation, is
composed of 256 bits numbered from 1 to 256 and is repeated with the frequency of 8 kHz.
Successive bits: 1
÷
8, 9
÷
16, 17
÷
24, ..., and 249
÷
256 form 32 channels, 64 kbit/s each. These
channels are located in 32 time slots numbered from 0 to 31.
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
Fig. 14.
Frame of the 2048 kbit/s signal
For transmission of digital signals only time slots 1 - 15 and 17 – 31 are used.
The slot 0 is used for transporting the frame synchronization pattern, service bits and
CRC-4 cyclic code remainder bits (if the generation option is set). The sixteenth slot dedi-
cated to signalling is not used.
The device allows setting the option of generation of CRC-4 code and multiframe syn-
chronisation signal. The device is factory configured in such a way that the remainder of
CRC-4 code and the pattern of multiframe synchronisation are not added to outgoing frame.
To enable the function of adding the remainder of CRC-4 code, it is necessary to short JP16
contacts on position 17 (Fig. 15), whereas adding the multiframe synchronisation pattern is
forced by shorting JP16 contacts on position 3. To activate these settings it is necessary to
restart the device or initialise it by momentary shorting the RESET contacts.
PMC
PMC
AL
T
E
RA
ATMEL
17 3 4 5
RESET
J 16
P
Fig. 15.
Jumpers for enabling generation of CRC-4 cyclic code and multiframe
synchronisation signal
