Lake Shore Model 460 Gaussmeter User’s Manual
4-4
Remote Operation
4.1.3
Status Registers
There are two status registers: the Status Byte Register described in Paragraph 4.1.3.1, and the
Standard Event Status Register in Paragraph 4.1.3.2.
4.1.3.1
Status Byte Register and Service Request Enable Register
The Status Byte Register consists of a single byte of data containing six bits of information about
the condition of the Model 460.
STATUS BYTE REGISTER FORMAT
Bit –
7
6
5
4
3
2
1
0
Weighting –
128
64
32
16
8
4
2
1
Bit Name –
Not Used
SRQ
ESB
OVI
Not Used
ALM
RNG
FDR
If the Service Request is enabled, any of these bits being set will cause the Model 460 to pull the
SRQ management low to signal the BUS CONTROLLER. These bits are reset to zero upon a serial
poll of the Status Byte Register. These reports can be inhibited by turning their corresponding bits
in the Service Request Enable Register to off.
The Service Request Enable Register allows the user to inhibit or enable any of the status reports
in the Status Byte Register. The QSRE command is used to set the bits. If a bit in the Service
Request Enable Register is set (1), then that function is enabled. Refer to the QSRE command
discussion.
Service Request (SRQ) Bit (6)
– Determines whether the Model 460 is to report via the SRQ line
and four bits determine which status reports to make. If bits 0, 1, 2, 4 and/or 5 are set, then the
corresponding bit in the Status Byte Register will be set. The Model 460 will produce a service
request only if bit 6 of the Service Request Enable Register is set. If disabled, the Status Byte
Register can still be read by the BUS CONTROLLER by means of a serial poll (SPE) to examine
the status reports, but the BUS CONTROLLER will not be interrupted by the Service Request.
The QSTB common command will read the Status Byte Register but will not clear the bits.
The bit assignments are discussed below as they pertain to the Status Byte Register. These reports
can only be made if they have been enabled in the Service Request Enable Register.
Standard Event Status (ESB) Bit (5)
– When bit 5 is set, it indicates if one of the bits from the
Standard Event Status Register has been set. (Refer to Paragraph 4.1.3.2.)
Overload Indicator (OVI) Bit (4)
– If the display has an overload condition on any channel, this bit
is set and a Service Request is issued if enabled.
Alarm (ALM) Bit (2)
– This bit is set when an alarm condition exists on any channel. This condition
will latch until acknowledged by the bus controller.
Range Change (RNG) Bit (1)
– Range changed in Auto Range mode on any channel.
Field Data Ready (FDR) Bit (0)
– When this bit is set, new valid field readings are available.
4.1.3.2
Standard Event Status Register and Standard Event Status Enable Register
The Standard Event Status Register supplies various conditions of the Model 460.
STANDARD EVENT STATUS REGISTER FORMAT
Bit –
7
6
5
4
3
2
1
0
Weighting –
128
64
32
16
8
4
2
1
Bit Name –
PON
Not Used
CME
EXE
DDE
QYE
Not Used
OPC
Bits 2 and 6 are not used. The user will only be interrupted with the reports of this register if the bits
have been enabled in the Standard Event Status Enable Register and if bit 5 of the Service
Request Enable Register has been set.
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