BT85x Series
Datasheet
Embedded Wireless Solutions Support Center:
http://ews-support.lairdtech.com
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11
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Figure 2: PCM timing diagram (Short-Frame Sync, Master Mode)
Table 9: PCM Interface timing specifications (Short-Frame Sync, Master Mode)
Ref No.
Characteristics
Minimum
Typical
Maximum
Unit
1
PCM bit clock frequency
-
-
12
MHz
2
PCM bit clock LOW
41
-
-
ns
3
PCM bit clock HIGH
41
-
-
ns
4
PCM_SYNC setup
0
-
25
ns
5
PCM_OUT delay
0
-
25
ns
6
PCM_IN setup
8
-
-
ns
7
PCM_IN hold
8
-
-
ns
8
Delay from rising edge of PCM_BCLK during last bit
period to PCM_OUT becoming high impedance
0
-
25
ns
Figure 3
and
Table 10
shows PCM Timing Diagram and Specifications for the slave mode of short-frame.
Figure 3: PCM timing diagram (Short-Frame Sync, Slave Mode)
Table 10: PCM Interface timing specifications (Short-Frame Sync, Slave Mode)
Ref No.
Characteristics
Minimum
Typical
Maximum
Unit
1
PCM bit clock frequency
-
-
12
MHz
2
PCM bit clock LOW
41
-
-
ns
