Kvaser PCIcan Hardware Reference Manual
15(21)
Kvaser AB, Mölndal, Sweden — www.kvaser.com
Address area #
Type
Size (bytes)
Used for
0
I/O
128
AMCC registers.
Described in the S5920
manual.
1
I/O
128
SJA1000 circuits
0
– 0x1f: SJA1000 #1
0x20
– 0x3F: SJA1000 #2
0x40
– 0x5F: SJA1000 #3
0x60
– 0x7F: SJA1000 #4
2
I/O
8
Xilinx registers
Address area number 1, the one used for the SJA1000’s, is further subdivided into four areas
of 32 bytes each; one for each (possible) SJA1000.
The S5920 is operated in pass-thru operation, passive mode.
To configure the address areas, the value 0x80808080 should be written into the PCI PASS-
THRU CONFIGURATION REGISTER (PTCR) register. This sets all regions to use 0 wait
states and to use the PTADR signal.
5.15 Interrupts
The PCIcan uses one PCI bus interrupt, INTA#. It is asserted whenever one or more
SJA1000’s have their interrupts active. To reset an active interrupt, read the interrupt status
register in all present SJA1000s
– the interrupt of the corresponding SJA1000 will then
automatically clear.
To check the status of the interrupt line, test the INTERRUPT ASSERTED bit (number 23) in
the INTCSR register in the S5920.
To enable or disable interrupts from the PCIcan, use the ADD-ON INTERRUPT PIN ENABLE
(bit 13) in the INTCSR register in the S5920.
5.16 Registers in the Xilinx
The Xilinx FPGA implements a few registers.
Address
offset
Register
Usage
0
– 6
Reserved, do not use
7
VERINT
Bit 7 - 4 contains the revision number of the
FPGA configuration. 15 is the first revision, 14 is
the next, and so on.
The current FPGA revision number is 14 (which is read from the VERINT register as
1110xxxx). Future revisions (13, 12, 11, …) will remain compatible with revision 14.
5.17 PCI Configuration Data