mITX-SKL-H – User Guide, Rev.1.1
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Function
Second level Sub-screen / Description
PEG Port
Configuration>
(continued)
PWG Port Feature
Configuration>
Detect non-compliance
Device>
Enable/disable non-compliance PCI
express device in PEG
Program PCIe ASPM
After OpROM>
Enable/disable PCIe ASPM programming before or after OpROM
Enable –progrmmed after OpROM.
Disable –programmed before OPROM
Program Static
Phase1 Eq>
Program phase1 presets/CTLEp
Gen3 Root Port
Preset Value for Each
Lane>
Select the lane >
(lane 0 to 15)
Display value for selected lane.
Gen3 End Point
Preset Value for Each
Lane>
Gen3 Endpoint Hint
Value for Each Lane>
Gen3 RXCTLE
Control>
Select
(Bundle0– 7 or RXCTLE Override)
Display Gen3 RxCTLE setting for bundle
Always Attempts SW
EQ>
Always attempts SW EQ even if it has been performed once
Number of Presets to
Test>
Select the number of presets to test
Chose( 7, 3, 5, 8) or ( 0-9) or ( Auto for default value)
Note: Do not change from the default unless debugging.
Allows PERST# GPIO
Usage>
Enable/disable GPIO based resets to PEG endpoint(s) during margin search
SW EQ Enable VOC>
Select jitter & VOC test mode (default) or jitter only test mode
Jitter Dwell Time>
Displays PEG Gen3 preset search dwell time [0-65535] in μs
Jitter Error Target>
Displays margin search error target value [1-65535]
VOC Dwell Time>
Displays VOC margin search dwell time [0..65535]
VOC Error Target>
Display VOC margin search error target value [1-65535]
Generate BDAT PEG
Margin Data>
Enable/disable BDAT PCIe margin tables
PCI Rx CEM Test
Mode>
Enable/disable PEG Rx CEM loopback mode
PCIe Spread
Spectrum Clocking>
Enable/disable spreader clocking for compliance testing
Stop Grant
Configuration>
Set automatic or manual stop grant configuration
VT-d>
Enable/disable VT-d capabilities
Chap Device
(B0:D4:F0)>
Enable/disable SA CHAP device
Thermal Device
(B0:D4:F0)>
Enable/disable SA C thermal device
