mITX-SKL-H – User Guide, Rev.1.1
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Pin
Signal
Type
Note
33
LVDS B2-
LVDS
34
LVDS B2+
LVDS
35
LVDS BCLK-
LVDS
36
LVDS BCLK+
LVDS
37
LVDS B3-
LVDS
38
LVDS B3+
LVDS
39
GND
PWR
40
GND
PWR
The on-board LVDS connector supports single and dual channel, 18/24 bit SPWG panels, up
to a resolution of 1600x1200 px or 1920x1080 px and with limited frame rate up to
1920x1200 px.
Signal Description
Signal
Description
LVDS A0…A3
LVDS A Channel data
LVDS ACLK
LVDS A Channel clock
LVDS B0…B3
LVDS B Channel data
LVDS BCLK
LVDS B Channel clock
BKLTCTL
Backlight control, PWM signal to implement voltage in the range 0 V-3.3 V.
BKLTEN#
Backlight enable signal (active low)
VDD ENABLE
Output display enable
LCDVCC
VCC supply to the display. 5 V or 3.3 V (1 A maximum) selected in BIOS setup menu.
Power sequencing depends on LVDS panel selection.
DDC CLK
DDC Channel Clock
GND
Power Supply GND signal
Windows API will be available to operate the BKLTCTL signal. Some Inverters have a limited
voltage range 0 V - 2.5 V for this signal: If voltage is > 2.5 V the inverter might latch up. Some
inverters generate noise on the BKLTCTL signal, causing LVDS transmission to fail
(corrupted picture on the display). By adding a 1 K
Ω
resistor in series with this signal,
mounted at the inverter end of the cable kit, noise is limited and the picture is stable.
If the Backlight Enable is required to be active high then check the BIOS setup menus.
